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Clockless Chips

This document discusses asynchronous (clockless) circuits. It begins with an introduction to the concept of a clock and how synchronous circuits rely on a global clock signal. Problems with synchronous circuits include being limited by the slowest component and high power consumption from the clock. Asynchronous circuits do not have a global clock and instead use handshaking signals to synchronize operations, allowing different parts to work at individual speeds. Advantages of asynchronous circuits include increased speed, reduced power consumption, and less electromagnetic noise. Some challenges to asynchronous design include greater design difficulties and lack of tools and training for engineers.

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vishal patyal
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427 views23 pages

Clockless Chips

This document discusses asynchronous (clockless) circuits. It begins with an introduction to the concept of a clock and how synchronous circuits rely on a global clock signal. Problems with synchronous circuits include being limited by the slowest component and high power consumption from the clock. Asynchronous circuits do not have a global clock and instead use handshaking signals to synchronize operations, allowing different parts to work at individual speeds. Advantages of asynchronous circuits include increased speed, reduced power consumption, and less electromagnetic noise. Some challenges to asynchronous design include greater design difficulties and lack of tools and training for engineers.

Uploaded by

vishal patyal
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 23

BY-

VISHAL PATYAL
3050060122
An Introduction
Talk Flow:
Introduction.
Concept of clock.
Working of synchronous circuits.
Problem of synchronous circuits.
Concept of clockless chip.
Working of asynchronous circuit.
Advantages of clockless design.
Applications.
Challenges.
Conclusion.
References.

3
Concept of clock
CLOCK:
Tiny crystal oscillator.

Sets basic rhythm used throughout the machine.

ADVANTAGES:

 Signals the device of the chip when to i/p or o/p.

This functionality makes designing of synchronous chip easier.

4
Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
5
continued…
This circuit looks for a particular signal(leading edge) of
the clock.

All actions takes place only at this part of clock cycle.

When transferring data to registers the computation


settles down and wait till the next leading edge

Designer’ challenge: to complete one operation before


next clock tick.

6
Problems of synchronous
circuit
Speed
 chip can only work as fast as its slowest component.
 leads to wasting of computation time.
 to traverse the chip’s longest wire in one clock cycle.
 so one alternate solution: Second clock incur

overhead and power consumption.

7
continued…
Power consumption
Consume more power than any other component.

Not associated with direct computation.

If no. of transistors more power consumption more.

EMI(Electro Magnetic Interference)

It is more in synchronous elements.

8
9
Concept of Clockless
chip
Clockless chip/asynchronous/self timed/event driven.

Do not have a global clock.

Rely upon handshaking signals , hand-off signals and


sometimes a local clock to synchronize all actions.

Draw power only when there is useful work to do.

10
Continued…
Chip can run at the average speed of all
components.

Different part work at different speeds.

Hand-off the result immediately.

Very low Electro Magnetic Noise.

11
Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
12
Continued…
TYPES OF
IMPLEMENTATION:
BOUNDED DELAY METHOD
similar to synchronous design

DELAY INSENSITIVE METHOD


opposite of bounded delay method

NULL CONVENTIONAL LOGIC(NCL)


it uses a NULL state when data is in reset
phase,
as opposed to data in set phase.
13
Continued…
BOUNDED DELAY METHOD:
Simplest implementation of asynchronous
design.

Assumption: we know the largest amount of


time for each component to perform its task.

Very similar to synchronous design.

Prototype delay is introduced here.


14
Continued…
DELAY INSENSITIVE METHOD:
Does not assume
any bound on time.

One method of this


type is : Dual-rail
method.

15
Continued…
NULL CONVENTIONAL LOGIC:
NCL integrates data transformation and
control into a single expression.

It gives solutions for power , noise and system


integration issue.

NCL uses threshold gates with hysteresis.

16
Advantages of clockless design:
Increase in speed

Reduced power consumption

Less Electro Magnetic Noise

Flexible design

Provide superior encryption


17
Applications:
In the lab.

In mobile electronics.

In personal computers.

In encryption devices.

18
19
Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
Challenges
Design difficulties.

Lack of good tools.

Engineers are not trained in these fields.

Academically, no courses available.

20
Conclusion:
Clocks are getting faster , while chips are
getting bigger, both of which make clock
distribution harder. There are also various
other problems associated with it. So we could
only get out of it , if more focus , especially at
the university level is given to the
asynchronous design. It is certainly a challenge
, but as software community is moving
towards concurrency, hardware community
must move to incorporate asynchronous logic.

21
References:
 David Geer , “ Is it time for clock less chips?
 http://www.google.com
 http://www.howstuffworks.com
 http://www.guruji.com

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QUERIES??

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