The time delay of the five segments in a certain pipeline are

as follows:
t1=30 ns,
t2=70 ns,
t3=20 ns,
t4=25 ns,
t5=35 ns.
The interface registers delay time tr=5 ns.

How long wold it ta!e to add "00 pairs of nm#ers in the
pipeline$.
Solve the following question
Memory Organization
12.1 Memory Hierarchy
12.2 Main Memory
12.3 Auxiliary Memory
12.4 Associative Memory
12.5 ache Memory
12.! "irtual Memory
12.# Memory management har$ware
Memory Hierarchy
%he overall goal of using a memory hierarchy is to o&tain the
highest'(ossi&le average access s(ee$ while minimi)ing the
total cost of the entire memory system.
Micro(rogramming* refers to the existence of many (rograms in
$ifferent (arts of main memory at the same time .
Main memory
+,M hi(
Memory A$$ress Ma(
Memory onfiguration -case stu$y.*
+equire$* 512 &ytes +,M / 512 &ytes +AM
Availa&le* 512 &yte +,M / 120 &ytes +AM
%he $esigner of a com(uter system must calculate the
amount of memory require$ for the (articular a((lication
an$ assign it to either +AM or +,M.
%he interconnection &etween memory an$ (rocessor is then
esta&lishe$ from 1nowle$ge of the si)e of memory nee$e$
an$ the ty(e of +AM an$ +,M chi(s availa&le .
%he a$$ressing of memory can &e esta&lishe$ &y means
of a ta&le that s(ecifies the memory a$$ress assigne$ to
each chi( .
%he ta&le2 calle$ a memory a$$ress ma(2 is a (ictorial
re(resentation of assigne$ a$$ress s(ace for each chi( in
the system .
Memory A$$ress Ma(
1288
RAM 1
CS1
AD7
WR
RD
CS2
1288
RAM 2
CS1
AD7
WR
RD
CS2
1288
RAM 4
CS1
AD7
WR
RD
CS2
1288
RAM 3
CS1
AD7
WR
RD
CS2
1288
ROM
CS1
CS2
AD9
Data
Data
Data
Data
Data
CPU
WR RD 16 - 11 10 9 8 7 - 1
Address bus
Data bus
Decder
3 2 1 0
1-7
8
9
Memory connections
to the 34
Associative Memory
Associative Memory
%he time require$ to fin$ an item store$ in memory can &e
re$uce$ consi$era&ly if store$ $ata can &e i$entifie$ for access
&y the content of the $ata itself rather than &y an a$$ress.
A memory unit access &y content is calle$ an associative
memory or ontent A$$ressa&le Memory -AM.. %his ty(e of
memory is accesse$ simultaneously an$ in (arallel on the &asis
of $ata content rather than s(ecific a$$ress or location.
5hen a wor$ is written in an associative memory2 no a$$ress is
given. %he memory is ca(a&le of fin$ing an em(ty unuse$
location to store the wor$. 5hen a wor$ is to &e rea$ from an
associative memory2 the content of the wor$ or (art of the
wor$ is s(ecifie$.
%he associative memory is uniquely suite$ to $o (arallel
searches &y $ata association. Moreover2 searches can &e $one
on an entire wor$ or on a s(ecific fiel$ within a wor$.
Associative memories are use$ in a((lications where the
search time is very critical an$ must &e very short.
Har$ware ,rgani)ation
Argument register -A (
6ey register -6 (
Associative memory
array an$ logic
m wor$s
n &its (er wor$
M
Match
register
7n(ut
5rite
+ea$
,ut(ut
Associative memory of an m wor$2 n cells (er wor$
A
1

11
A
n
A
8
61 6n 68

18

1n
i1 i8 in

m1

m8

mn
M1
Mm
M
i
9it 1 9it n 9it 8
5or$ 1
5or$ m
5or$ i
,ne ell of Associative Memory
+ S
Match
logic
7n(ut
+ea$
5rite
,ut(ut
%o Mi
68 Ai
:i8
%eglect the & #its and compare the argment in ' with the #its
stored in the cells of the words.
(ord i is e)al to the argment in ' if
Two #its are e)al if they are #oth " or 0
*or a word i to #e e)al to the argment in ' we mst have all +
,

varia#les e)al to ".
This is the condition for setting the corresponding match #it -
i
to ".
Match logic
;ow inclu$e the 1ey &it 6
8
in the com(arison logic
%he requirement is that if 6
8
<=2 the corres(on$ing &its of A
8
an$
nee$ no com(arison. ,nly when 6
8
<1 must &e com(are$. %his
requirement is achieve$ &y ,+ ing each term with 6
8
%he match logic for wor$ i in an associative memory can now &e
ex(resse$ &y the following 9oolean function.
7f we su&stitute the original $efinition of x
8
2 the a&ove 9oolean
function can &e ex(resse$ as follows*
5here is a (ro$uct sym&ol $esignating the A;> o(eration of all n terms.
ont.
Match ?ogic cct.
* '
i"
*
i"
'
1 &
1
* '
i2
*
i2
'
2 &
2
* '
in
*
in
'
n &
n
-
i
+ea$ ,(eration
.f more than one word in memory matches the nmas!ed argment
field, all the matched words will have "/s in the corresponding #it
position of the match register .
.t is then necessary to scan the #its of the match register one at
a time. The matched words are read in se)ence #y applying a
read signal to each word line whose corresponding -
i
#it is a ".
.f only one word may match the nmas!ed argment field, then
connect otpt -
i
directly to the read line in the same word
position ,
The content of the matched word will #e presented atomatically
at the otpt lines and no special read command signal is
needed.
.f we e+clde words having 0ero content, then all 0ero otpt will
indicate that no match occrred and that the searched item is not
availa#le in memory.
5rite ,(eration
.f the entire memory is loaded with new information at once,
then the writing can #e done #y addressing each location in
se)ence .
The information is loaded prior to a search operation .
.f nwanted words have to #e deleted and new words inserted
one at a time, there is a need for a special register to
distingish #etween active an inactive words .
This register is called 1Tag 2egister .
' word is deleted from memory #y clearing its tag #it to 0 .
ache Memory
ache Memory
3ocality of reference
The references to memory at any given interval of time tent to #e
contained within a few locali0ed areas in memory.
.f the active portions of the program and data are placed in a fast
small memory, the average memory access time can #e redced.
Ths, redcing the total e+ection time of the program. 4ch a
fast small memory is referred to as 15ache -emory6.
The performance of the cache memory is measred in terms of a
)ality called 1Hit 2atio6.
(hen the 578 refers to memory and finds the word in cache, it
prodces a hit. .f the word is not fond in cache, it conts it as
a miss.
The ratio of the nm#er of hits divided #y the total 578 references
to memory 9hits : misses; is the hit ratio. The hit ratios of 0.<
and higher have #een reported
The average memory access time of a compter system can #e
improved considera#ly #y se of cache.
The cache is placed #etween the 578 and main memory. .t is the
faster component in the hierarchy and approaches the speed of
578 components.
(hen the 578 needs to access memory, the cache is e+amined. .f
it is fond in the cache, it is read very )ic!ly.
.f it is not fond in the cache, the main memory is accessed.
' #loc! of words containing the one ,st accessed is then
transferred from main memory to cache memory .
*or e+ample,
' compter with cache access time of "00ns, a main memory
access time of "000ns and a hit of 0.< prodce an average access
time of 200ns. This is a considera#le improvement over a similar
compter withot a cache memory, whose access time is "000ns.
ache Memory
The #asic characteristic of cache memory is its fast access time.
Therefore, very little or no time mst #e wasted when searching
for words in the cache.
The transformation of data from main memory to cache memory
is referred to as a 1-apping 7rocess6.
There are three types of mapping procedres are availa#le.
= 'ssociative -apping
= >irect -apping
= 4elf ? 'ssociative -apping.
ache Memory
5onsider the following memory organi0ation to show mapping
procedres of the cache memory .
The main memory can stores 32! word of "2 #its each .
The cache is capa#le of storing 5"2 of these words at any given
time .
*or every word stored in cache, there is a dplicate copy in main
memory .
The 578 commnicates with #oth memories
.t first sends a "5 ? #it address to cache .
.f there is a hit, the 578 accepts the "2 #it data from cache
.f there is a miss, the 578 reads the word from main memory and
the word is then transferred to cache .
ache Memory
Associative Ma((ing
%he associative ma((ing stores &oth the a$$ress an$ content -$ata.
of the memory wor$ .
A 34 a$$ress of 15 &its is (lace$ in the argument register an$
associative memory is searche$ for a matching a$$ress .
7f the a$$ress is foun$2 the corres(on$ing 12 &it $ata is rea$ an$
sent to the 34 .
7f no match occurs2 the main memory is accesse$ for the wor$.
%he a$$ress @ $ata (air is then transferre$ to associative cache
memory .
7f the cache is full2 it must &e $is(laye$2 using re(lacement algorithm.
:7:, may &e use$ .
'rgment register
@ctal
>irect Ma((ing
The "5A#it 578 address is divided into two fields.
The < least significant #its constitte the inde+ field and the
remaining B #its form the tag fields.
The main memory needs an address #t incldes #oth the tag and
the inde+ #its.
The cache memory re)ires the inde+ #it only i.e., < #its.
There are 2
!
words in the cache memory C 2
n
words in the main
memory.
e.g: ! = <, n = "5
>irect Ma((ing
00000
6710
>irect Ma((ing
Dach word in cache consists of the data word and it associated tag .
(hen a new word is #roght into cache, the tag #its store along
data
(hen the 578 generates a memory re)est, the inde+ field is
sed in the address to access the cache .
The tag field of the 578 address is e)al to tag in the word from
cacheE there is a hit, otherwise miss .
How can we calculate the wor$ si)e of the
cache memoryA
>irect Ma((ing
Set @ Associative Ma((ing
.n set ? 'ssociative mapping, each word of cache can store two or
more words of memory nder the same inde+ address.
Dach data word is stored together with its tag and the nm#er of
tag ? data items in one word of cache is said to form a set.
Dach inde+ address refers to two data words and their associated tags.
Dach tag re)ires B #its C each data word has "2 #its, so the word
length is 29B:"2; =3B #its
'n inde+ address of < #its can accommodate 5"2 cache words. .t
can accommodate "02F memory words.
(hen the 578 generates a memory re)est, the inde+ vale of the
address is sed to access the cache.
The tag field of the 578 address is compared with #oth tags in the
cache.
Set @ Associative Ma((ing
The most common replacement algorithms are :
2andom replacement
*.*@
3east 2ecently 8sed 9328 (
5riting into cache
(riteA#ac! method
(riteAthrogh method 9The simplest C commonly sed way;
there are two writing methods that the system can proceed.
pdate main memory with every memory write operation, with cache memory
#eing pdate in parallel if it contains the word at the specified address.
This method has the advantage that main memory always contains the
same data as the cache.
.n this method only the cache location is pdated dring a write operation.
The location is then mar!ed #y a flag so that later when the word is
removed from the cache it is copied into main memory.
The reason for the writeA#ac! method is that dring the time a word resides
in the cache, it may #e pdated several times.