VHDL 0

INTRODUCTION TO
VHDL
K H Wong
khwong@cse
2609-8397,
Room 907 SHB-Engineering building
http://www.cse.cuhk.edu.hk/~khwong/www2/ceng3430/ceng3430.html
VHDL 0 (v.3A) : Introduction 1
CENG3430 Rapid Prototyping of Digital Systems

You will learn:
The hardware description language VHDL
Techniques to build a Central Processing Unit (CPU)
High speed logic circuits analysis: time delay estimation, testing,
power supply stability, etc.

1 entity and2 is port (a,b : in std_logic;
2 c : out std_logic);
3 end and2
4 architecture and2_arch of and2
5 begin
6 c <=a and b;
7 end and2_arch

Write VHDL code, then
it will generate the
hardware chip automatically
Example: A VHDL Program
VHDL 0 (v.3A) : Introduction 2
A QUICK RUN
THROUGH
Overview
VHDL 0 (v.3A) : Introduction 3
Overview
What is VHDL used for?
To design
Hardware systems (an industrial standard)
Microprocessors: Arm7 etc
Design new Digital systems: e.g. mobile phone, camera chips
VHDL 0 (v.3A) : Introduction 4
Motivations
Learn to design digital systems.
Provide knowledge for you to :
Design products:
Mp3, mp4 players, portable games, mobile phones.
Advanced examples
Image processing
Computer vision
Super computer
Start a business.
VHDL 0 (v.3A) : Introduction 5
Examples of digital system design
Mass products
Mp3, mp4, video players
PDA, mobile phones
Novel products
Wearable computer
Robots
Research
Real time edge detection for
computer vision


VHDL 0 (v.3A) : Introduction 6
www.wearable-consult.com/images/buergy_hwd.jpg

www.cnn.com/.../06/10/mars.rover/index.html
To learn

Design digital processing components using
programmable logic
Two existing Methods
(a) Schematic, (too complicated
But is suitable to describe the top level design like a data flow block diagram
(b) Language (e.g. VHDL--Very-High-Speed-Integrated-Circuits
Hardware Description Language): Each module in the schematic
can be written in VHDL.
VHDL 0 (v.3A) : Introduction 7
DIGITAL DESIGN
Work Flow
VHDL 0 (v.3A) : Introduction 8
Digital Design Work Flow
Idea generation
Drafting on paper
Design the chip (use VHDL)
Test
Manufacturing production line design
Quality control


VHDL 0 (v.3A) : Introduction 9
WE USE IN OUR LAB
Hardware: FPGA (Field Programmable Gate Array)
The hardware can be reprogrammable , so you can change your design
rapidly and easily with no additional hardware manufacturing cost.
Software: VHDL (Very-High-Speed-Integrated-
Circuits Hardware Description Language)
VHDL 0 (v.3A) : Introduction 10
Re-programmable Hardware: FPGA Field
Programmable Gate Array
So what is inside an FPGA

IOB=Input/Output block
CLB=Configurable Logic
block (static ram based)
Change the CLBs to get
the desired functions
VHDL 0 (v.3A) : Introduction 11
From http://www.alldatasheet.co.kr/datasheet-
pdf/pdf_kor/49173/XILINX/XCS10-3PC84C.html
Inside a CLB (Configurable Logic block )
The CLB is a fixed design but you can change the logic
function for generating output from input G1-G4 by
reprogramming the bits in the logic function lookup table.
This will change the overall logic function of the CLB
Re-programming the logic table
VHDL 0 (v.3A) : Introduction 12
http://www.design-reuse.com/news_img/20100913_1.gif
http://pldworld.biz/html/technote/pldesignline/bobz-02.gif
CLB
FPGA CLB
(Configurable Logic block )
Software: to program an FPGA

VHDL 0 (v.3A) : Introduction 14
1 entity and2 is port (a,b : in std_logic;
2 c : out std_logic);
3 end and2
4 architecture and2_arch of and2
5 begin
6 c <=a and b;
7 end and2_arch

Use a schematic: (Top level
design to merge modules)
Use a language VHDL (for each
module)
or/and

VHDL 0 (v.3A) : Introduction 15
1 entity and2 is port (a,b : in std_logic;
2 c : out std_logic);
3 end and2
4 architecture and2_arch of and2
5 begin
6 c <=a and b;
7 end and2_arch

Development cycle
VHDL language
Schematic (diagram)
Timing simulation

VHDL 0 (v.3A) : Introduction 16
Summary of VHDL
For hardware Design
Parallel language (not sequential)
Different! (not the same as C++ or Java)
VHDL is the industrial standard for CE.
VHDL 0 (v.3A) : Introduction 17
An example: And gate in VHDL
1 entity and2 is port (a,b : in std_logic;
2 c : out std_logic);
3 end and2
4 architecture and2_arch of and2
5 begin
6 c <=a and b;
7 end and2_arch

VHDL 0 (v.3A) : Introduction 18
a
b
c
The chip
C<=a and b
COMPUTER
ENGINEERING MARKET
and VHDL
VHDL 0 (v.3A) : Introduction 19
Major high-tech companies , a comparison in 2011 (from wiki) Wiki: 2009
2,589.6,16,000http://money.163.com 500,
(2011-08-25)


Company Apple IBM Microsoft Intel HP TSMC


(largest
asset in
Taiwan
stock
market)
Huawei

(Telecom
equipmt,
China
large
private
company)
Revenue
US Billion
65.23 99 69.94 43.6 99.87 13.98 21.8
Asset 75.1 113.5 108.7 63.2 124.5 20.43 Not
known
Profit
US Billion
14.01 14 23.15 11.46 14.83 5.55 2.67
VHDL 0 (v.3A) : Introduction 20
Major companies , a comparison in 2011
(from wiki)

Company Boeing Nestle Honda Toyota Ford HS
BC
Len
ovo
BP Sony
Revenue
US Billion
68.5 125 120 235 128 98.
9
21.
59
308
.9
86.64
Asset 64.3 126 125 370 166 24
54
10.
71
272
.2
155.9
4
Profit
US Billion
3.3 39 1.39 5.07 6.56 13.
15
0.2
73
3.3 2.96
VHDL 0 (v.3A) : Introduction 21
TSMC (Taiwan Semicon. Manufacturing Comp.)

http://www.tsmc.com
From Wiki:
Has the largest asset in Taiwan stock market,
World's largest dedicated independent semiconductor foundry.
Products: Apple iphone5's A6-cpu
Relation to VHDL
Design ideaWrite VHDL TSMC chips
VHDL 0 (v.3A) : Introduction 22
Huawei Technologies Co. Ltd
http://www.huawei.com/en/

From wiki:
Telecom equipment manufacture
China large private company--http://money.163.com 500 (2011-08-
25)
Products: the second-largest supplier of mobile
telecommunications infrastructure equipment in the
world (after Ericsson).
VHDL 0 (v.3A) : Introduction 23
References
See course web page
Digital Design Principles and Practices by John F.
Wakerly, Prentice Hall (third Edition) 2001 includes
Xilinx student edition).
http://www.alldatasheet.com/
www.eece.unm.edu/course/ece338/Lectures/basi
c-fpga-arch-xilinx.ppt
High-Speed Digital Design: A Handbook of Black
Magic by Howard W. Johnson and Martin Graham,
Prentice Hall, 1993. Around US$20 dollars.
VHDL 0 (v.3A) : Introduction 24
TRI-STATE LOGIC
A revision:
The concept of tri-state logic is essential in
computer design, so we want to revise these
techniques before we move on.

VHDL 0 (v.3A) : Introduction 25
Appendix 1:Tri-state logic
**At the float state, the wire is cut



VHDL 0 (v.3A) : Introduction 26
Input
Output
enable (OE)
Output
Input OE (input) Output
0 0 Z(Float)
1 0 Z(Float)
0 1 0
1 1 1
Tri-state equivalent circuit
(using output connect/cut view)

VHDL 0 (v.3A) : Introduction 27
Input
Output
enable (OE)
Output
Input
Output
enable (OE)
Output
OE=1, switch close
OE=0, switch open
Same as
Alternatively: we can treat the Tri-state equivalent
circuit using the Rout impedance view

VHDL 0 (v.3A) : Introduction 28
Input
Output
enable (OE)
Output
Input
Output
enable (OE)
Output
OE=1, Rout= small, (e.g. 50 )
OE=0, Rout=infinity (e.g. 10 M)
Same as
Rout
Student ID: ___________,Date:_____________
Name: _______________
Exercise0.1:Tri-state logic with pull up resistor



VHDL 0 (v.3A) : Introduction 29
Input1
Output-Enable (OE)
Output
5V
10K
Input1
Output-Enable
OE (input)
Output
0 0 ? ___
1 0 ? ___
0 1 ? ___
1 1 ? ___


**At float the wire is cut
Additional
exercise:
Use Rout (
Impedance
view) to
explain your
answer.
Exercise 0.2
Application 1 of Tri-state logic:
Input/Output pin
OE1 controls the traffic.
Fill in the cells with ?.
VHDL 0 (v.3A) : Introduction 30
Directional
control(OE1)
A
B
A
Output
Enable
OE1 (input)
B
0 0 ?
1 0 ?
? 1 0
? 1 1


Exercise 0.3
Application 2 of Tri-state logic:
Transceivers for I/O data pins
When T =1, A->B; T
controls the traffic,
when /OE=1, IO pins
A,B are disabled
Fill in the cells with ?.

VHDL 0 (v.3A) : Introduction 31
A
B
/OE
T
T A Output
Enable
/OE1
(input)
B Which
controls
which
1 0 0 ? ?
0 1 0 ? ?
? ? 1 Float ?
? Float 1 ? ?

All data-lines are transceiver buffers
A good controller will enable the CPU to
read/write RAM, and read ROM


VHDL 0 (v.3A) : Introduction 32
CPU data lines
transceivers
ROM
data
lines
RAM
data
lines
transceivers
transceivers
/OE1, T1
/OE2, T2
/OE3,
T3
Exercise 0.4 : List OE1,2,3 and T1,2,3 for
the followings cases
a) CPU writes to RAM:
/OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____
b) CPU reads from ROM
/OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____
c) CPU reads from RAM
/OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____


VHDL 0 (v.3A) : Introduction 33
CPU data lines
transceivers
ROM
data
lines
RAM
data
lines
transceivers
transceivers
/OE1, T1
/OE2, T2
/OE3,
T3
A
B
A B
B A
Exercise 0.5
Application 3 of Tri-state logic:
Selection of control signal (resolved logic)
Output depends on Input_A if OE is _?___
Output depends on Input_B if OE is _?___
Discuss the operation of this circuit.


VHDL 0 (v.3A) : Introduction
34
Input_B
Input_A
Output
OE
Exercise 0.6
Fill in ?.
Discuss the operation of this circuit.
Answer : nor-gate
VHDL 0 (v.3A) : Introduction 35
Output
OE2
5V
10K
OE1
0V
0V
OE1
OE2
Output
0 0 ?
1 0 ?
0 1 ?
1 1 ?