FET ( Field Effect Transistor)

1. Unipolar device i. e. operation depends on only one type of

charge carriers (h or e)
2. Voltage controlled Device (gate voltage controls drain
current)
3. Very high input impedance (~10
9
-10
12
O)
4. Source and drain are interchangeable in most Low-frequency
applications
5. Low Voltage Low Current Operation is possible (Low-power
consumption)
6. Less Noisy as Compared to BJT
7. No minority carrier storage (Turn off is faster)
8. Self limiting device
9. Very small in size, occupies very small space in ICs
10. Low voltage low current operation is possible in MOSFETS
11. Zero temperature drift of out put is possiblek
Few important advantages of FET over conventional Transistors
Types of Field Effect Transistors
(The Classification)
JFET
MOSFET (IGFET)
n-Channel JFET
p-Channel JFET
n-Channel
EMOSFET
p-Channel
EMOSFET
Enhancement
MOSFET
Depletion
MOSFET
n-Channel
DMOSFET
p-Channel
DMOSFET
FET
Figure: n-Channel JFET.
The Junction Field Effect Transistor (JFET)
Gate
Drain
Source
SYMBOLS
n-channel JFET
Gate
Drain
Source
n-channel JFET
Offset-gate symbol
Gate
Drain
Source
p-channel JFET
Figure: n-Channel JFET and Biasing Circuit.
Biasing the JFET
Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)
Operation of JFET at Various Gate Bias Potentials
P P
+
-
+
-
+
-
N
N
Operation of a JFET
Gate
Drain
Source
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:

The drain current is given by

(
(
(

|
.
|

\
|
=
2
2
2
2
DS
DS P GS
P
DSS
DS
V
V V V
V
I
I
(
(

|
.
|

\
|
=
2
2
P GS
P
DSS
DS
V V
V
I
I
2
1 and
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
Where, I
DSS
is the short circuit drain current, V
P
is the pinch off voltage
Output or Drain (V
D
-I
D
) Characteristics of n-JFET
Saturation (or Pinchoff) Region:
|
.
|

\
|
<
P GS DS
V V V
|
.
|

\
|
>
P GS DS
V V V
Figure: n-Channel FET for v
GS
= 0.
Simple Operation and Break down of n-Channel JFET
Figure: If v
DG
exceeds the breakdown voltage V
B
, drain current increases rapidly.
Break Down Region
N-Channel JFET Characteristics and Breakdown
Figure: Typical drain characteristics of an n-channel JFET.
V
D
-I
D
Characteristics of EMOS FET
Saturation or Pinch
off Reg.
Locus of pts where ( )
P GS DS
V V V =
Figure: Transfer (or Mutual) Characteristics of n-Channel JFET
2
1
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
I
DSS
V
GS (off)
=V
P
Transfer (Mutual) Characteristics of n-Channel JFET
JFET Transfer Curve
This graph shows the value of I
D
for a given
value of V
GS
Biasing Circuits used for JFET
Fixed bias circuit
Self bias circuit
Potential Divider bias circuit
JFET (n-channel) Biasing Circuits
2
1
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
0 , = = = + =
G GS GS G G GG
I Fixed V V R I V
D DS DD DS
P
GS
DSS DS
R I V V
V
V
I I
=
|
|
.
|

\
|
=
and
1
2
S
GS
DS
S DS GS
R
V
I
R I V
=
= + 0
For Self Bias Circuit
For Fixed Bias Circuit
Applying KVL to gate circuit we get
and
Where, V
p
=V
GS-off
& I
DSS
is Short ckt. I
DS
JFET Biasing Circuits Count
or Fixed Bias Ckt.
JFET Self (or Source) Bias Circuit
2
1 and
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
S
GS
P
GS
DSS
R
V
V
V
I =
|
|
|
.
|

\
|

2
1
0 2 1
2
= +
(
(
(

|
|
|
.
|

\
|
+
S
GS
P
GS
P
GS
DSS
R
V
V
V
V
V
I
This quadratic equation can be solved for V
GS
& I
DS
The Potential (Voltage) Divider Bias
0 1
2
=

|
|
|
.
|

\
|

S
GS G
P
GS
DSS
R
V V
V
V
I
DS GS
I V gives equation quadratic this Solving and
A Simple CS Amplifier and Variation in I
DS
with V
gs
FET Mid-frequency Analysis:
g
s
rd
gmvt
vi = vt
ii
io
vo
d
s
+ +
_
_
mid-frequency CE amplifier circuit
RD RL RTh vs

+

_

is
' ' o o i
vi m L L d D L vs vi
i s s i
i
i Th Th 1 2
i
Analysis of the CS mid-frequency circuit above yields:
v v Z
A = = -g R , where R = r R R A = = A
v v R + Z
v
Z = = R , where R = R R
i
(
(

L
o i
I vi
i L
o o
o d D P vi I
o i
seen by R
i Z
A = = A
i R
v p
Z = = r R A = = A A
i p
(
(

A common source (CS) amplifier is shown
to the right.
R
s
C
i
R
L
C
o
C
SS
v
i
v
o
+

+

v
s
+

_

_

_

i
o
i
i
D

S

G

V
DD

V
DD

R
1

R
SS

R
D

R
2

The mid-frequency circuit is drawn as follows:
the coupling capacitors (C
i
and C
o
) and the
bypass capacitor (C
SS
) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-t model
The resulting mid-frequency circuit is shown below.
FET Mid-frequency Analysis:
g
s
rd
gmvt
vi = vt
ii
io
vo
d
s
+ +
_
_
mid-frequency CE amplifier circuit
RD RL RTh vs

+

_

is
' ' o o i
vi m L L d D L vs vi
i s s i
i
i Th Th 1 2
i
Analysis of the CS mid-frequency circuit above yields:
v v Z
A = = -g R , where R = r R R A = = A
v v R + Z
v
Z = = R , where R = R R
i
(
(

L
o i
I vi
i L
o o
o d D P vi I
o i
seen by R
i Z
A = = A
i R
v p
Z = = r R A = = A A
i p
(
(

A common source (CS) amplifier is shown
to the right.
Rs
Ci
RL
Co
CSS
vi
vo
+
+
vs
+

_
_
_
io
ii
D

S

G

VDD

VDD

R1

RSS

RD

R
2

The mid-frequency circuit is drawn as follows:
the coupling capacitors (C
i
and C
o
) and the
bypass capacitor (C
SS
) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-t model
The resulting mid-frequency circuit is shown below.
Procedure: Analysis of an FET amplifier at mid-frequency:
1) Find the DC Q-point. This will insure that the FET is operating in the saturation
region and these values are needed for the next step.
2) Find g
m
. If g
m
is not specified, calculate it using the DC values of V
GS
as follows:




3) Calculate the required values (typically A
vi
, A
vs
, A
I
, A
P
, Z
i
, and Z
o
. Use the formulas for
the appropriate amplifier configuration (CS, CG, CD, etc).
( )
( )
DSS D
m GS P 2
GS P
D
m GS T
GS
GS
2I I
g = = V - V (for JFET's and DM MOSFET's)
V V
I
g = = V - V (for EM MOSFET's)
V
(Note: Uses DC value of V )
K
c
c
c
c
PE-Electrical Review Course - Class 4 (Transistors)
Example 7:
Find the mid-frequency values for A
vi
, A
vs
, A
I
, A
P
, Z
i
,
and Z
o
for the amplifier shown below. Assume that
C
i
, C
o
, and C
SS
are large.
Note that this is the same biasing circuit used in Ex. 2,
so V
GS
= -0.178 V.
The JFET has the following specifications:
I
DSS
= 4 mA, V
P
= -1.46 V, r
d
= 50 k
10 k
Ci
8 k
Co
CSS
vi
vo
+
+
vs
+

_
_
_
io
ii
D

S

G

18 V 18 V

800 k

2 k
500
400 k

FET Amplifier Configurations and
Relationships:
'
' ' m L
vi m L m L
'
m L
'
L d D L d D L SS L
i Th SS Th
m
o d D d D SS
m
i i i
vs vi vi vi
s i s i s i
i i i
I vi vi vi
L L L
P vi I vi I
CS CG CD
g R
A -g R g R
1 g R
R r R R r R R R R
1
Z R R R
g
1
Z r R r R R
g
Z Z Z
A A A A
R + Z R + Z R + Z
Z Z Z
A A A A
R R R
A A A A A
+
( ( (
( ( (

( ( (
( ( (

vi I
Th 1 2

A A
where R = R R
VCC
RD
S

R2
RSS
Rs
Ci
RL
Co
C2
vi
vo
+
+
vs
+
_
_
_
io
ii
Common Gate (CG) Amplifier
R1
D

G

Note: The biasing circuit is the same for each amp.
Rs
Ci
RL
Co
CSS
vi
vo
+
+
vs
+
_
_
_
io
ii
D

S

G

VDD

VDD

R1

RSS

RD

R2

Common Source (CS) Amplifier

R s
C i
v i
+
v s
+
_
_
i i
G

V DD

V DD

R 1

R SS

R 2

Common Drain (CD) Amplifier (also called source follower)

R L

C o

v o

+

_

i o

D

S

Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.
Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.
Figure: For v
GS
< V
to
the pn junction between drain and body is reverse biased and i
D
=0.
Figure: For v
GS
>V
to
a channel of n-type material is induced in the region under the gate.
As v
GS
increases, the channel becomes thicker. For small values of v
DS
,i
D
is proportional to v
DS.
The device behaves as a resistor whose value depends on v
GS.
Figure: As v
DS
increases, the channel pinches down at the drain end and i
D
increases more slowly.
Finally for v
DS
> v
GS
-V
to
, i
D
becomes constant.
Current-Voltage Relationship of
n-EMOSFET
Locus of points where
Figure: Drain characteristics
Figure: This circuit can be used to plot drain characteristics.
Figure: Diodes protect the oxide layer from destruction by static electric charge.
Figure: Simple NMOS amplifier circuit and Characteristics with load line.
Figure: Drain characteristics and load line
Figure v
DS
versus time for the circuit of Figure 5.13.
Figure Fixed- plus self-bias circuit.
Figure Graphical solution of Equations (5.17) and (5.18).
Figure Fixed- plus self-biased circuit of Example 5.3.
Figure The more nearly horizontal bias line results in less change in the Q-point.
Figure Small-signal equivalent circuit for FETs.
Figure FET small-signal equivalent circuit that accounts for the dependence of i
D
on v
DS
.
Figure Determination of g
m
and r
d
. See Example 5.5.
Figure Common-source amplifier.
For drawing an a c equivalent circuit of Amp.
Assume all Capacitors C1, C2, Cs as short
circuit elements for ac signal
Short circuit the d c supply
Replace the FET by its small signal model
Analysis of CS Amplifier
L gs m L o o
gs
o
v
R v g R i v
v
v
A
= =
= gain, Voltage
d D L L m
gs
o
v
r R R R g
v
v
A = = = ,
D d
D d
D d o
R r
R r
R r Z
+
= = imp., put Out
2 1
imp., Input R R R Z
G in
= =
A C Equivalent Circuit
Simplified A C Equivalent Circuit
Analysis of CS Amplifier with Potential Divider Bias
) R || (r g Av D d m =
D
R 10 r D, m
d
R g Av > ~
) R || (r g Av D d m =
This is a CS amplifier configuration therefore the
input is on the gate and the output is on the drain.
2 1 R || R Zi =
D d R || r Zo=
D d
D
10R r
R Zo
>
~