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E M L F D D - S C M A: Fficient Ajority Ogic Ault Etection With Ifference ET Odes FOR Emory Pplications

This document presents an efficient majority logic fault detection method for difference-set cyclic codes used in memory applications. The proposed Majority Logic Detector/Decoder (MLDD) significantly reduces memory access time when no error is present by using the majority logic decoder to directly detect failures. This approach has minimal area overhead and low extra power consumption compared to existing solutions that use a separate syndrome fault detector. The MLDD error detector module is also designed to be independent of code size to further reduce area costs.

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54 views10 pages

E M L F D D - S C M A: Fficient Ajority Ogic Ault Etection With Ifference ET Odes FOR Emory Pplications

This document presents an efficient majority logic fault detection method for difference-set cyclic codes used in memory applications. The proposed Majority Logic Detector/Decoder (MLDD) significantly reduces memory access time when no error is present by using the majority logic decoder to directly detect failures. This approach has minimal area overhead and low extra power consumption compared to existing solutions that use a separate syndrome fault detector. The MLDD error detector module is also designed to be independent of code size to further reduce area costs.

Uploaded by

venki
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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EFFICIENT MAJORITY LOGIC FAULT DETECTION WITH

DIFFERENCE-SET CODES FOR MEMORY APPLICATIONS


Presented
by
P.Venkatrao(Y12MTEC1204),
Under the guidance of
Dr. R.Sai Ram, M.E., Ph.D,
Professor and head.
INDEX
Abstract
Introduction
Literature survey
Existent Majority Logic Decoding(MLD) solutions
Proposed ML Detector/Decoder(MLDD)
Conclusion
Quires






ABSTRACT


This paper presents an error-detection method for difference-set
cyclic codes with majority logic decoding. Majority logic decodable codes
are suitable for memory applications due to their capability to correct a large
number of errors. However, they require a large decoding time that impacts
memory performance. The proposed fault-detection method significantly
reduces memory access time when there is no error in the data read. The
technique uses the majority logic decoder itself to detect failures, which
makes the area overhead minimal and keeps the extra power consumption
low.
INTRODUCTION

The impact of technology scaling is affecting the reliability of
memory applications not only in extreme radiation environments like
spacecraft and avionics electronics, but also at normal terrestrial
environments. Especially, SRAM memory failure rates are increasing
significantly, therefore posing a major reliability concern for many
applications
The reliability, availability, and serviceability (RAS) of the system
to perform to customer expectations are a strong function of how the system
is designed to respond to hard and soft failures





LITERATURE SURVEY

i. Desired ECC Properties
ii. Difference Set Cyclic Codes (DSCCS)
EXISTENT MAJORITY LOGIC DECODING(MLD) SOLUTIONS

Plain ML Decoder
Plain MLD With Syndrome Fault Detector (SFD)




Fig. 1. Memory system schematic with MLD.
PROPOSED ML DETECTOR/DECODER(MLDD)










Figure. 2. Schematic of the proposed MLDD
CONCLUSION

In this work, a fault-detection mechanism, MLDD, has been
presented based on ML decoding using the DSCCs .
The MLDD error detector module has been designed in a way that is
independent of the code size. This makes its area overhead quite
reduced compared with other traditional approaches such as the
syndrome calculation (SFD).
Scope for further work is instead of memory we use Nano memory
which provides smaller, faster, and lower energy devices which
allow more powerful and compact circuitry


Quires
?

THANK YOU

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