WL VCC T2 T4 T6 T5 T1 T3 BL

BL

BY Prof. Y. P. Jadhav Physics Department Smt. CHM college, Ulhasnagar - 3

Classification of memory
Memory can be classified on the basis of :

Physical characteristics
- erasable or non-erasable, volatile or nonvolatile memory

Mode of access
Sequential access and Random access memory

Fabrication technology
Bipolar and Unipolar (MOS)

Memory

Internal Memory Program storage Primary data storage

External Memory Secondary storage

Read Only Memory ROM

Read/ Write Memory RAM

Semi Random Access Flopy disk Hard disk CD ROM

Serial Access

Magnetic Tap Magnatic bubble CCD

Erasable storage

parmanent storage

Static RAM

Dynamic RAM

EPROM EEPROM

ROM PROM

Memories classified on the basis of mode of access (principal of operation) are:

Sequential memory (SAM) Read and Write memory (RWM or RAM) Read only memory (ROM) Content addressable memory (CAM)
A search key is supplied to read a content addressable memory e.g. Mobile

Sequential memory
In the sequential memory the locations are organized in sequence. The data is accessed (read or write) in sequential (serial) form, therefore the time required to access different memory locations is different. e.g. Magnetic tape audio/ video cassette, semiconductor sequential memory. Types of sequential semiconductor memory: Shift registers Charged coupled devices (CCD) Magnetic bubble memory.

Random Access Memory

Robert Dennard was the inventor of a type of computer memory called ram patented in 1968

data accessed in random fashion, so the time required for accessing (read or write) any memory location is same (equal). - RWM or RAM - ROM RWM or RAM : It is volatile memory. also known as read-write (RWM) memory. The alphanumerical data that is to be processed changes frequently. This type of data must be stored in RWM (instead of in ROM) so that it can be read by the processor, modified, if required, and then restored.

Types of RAWMs:
Static RAM Dynamic RAM NVRAM (Nonvolatile RAM)

Static RAM (SRAM): - made up of flipflops, - it stores the bit as a voltage. - each memory cell requires six transistors thus the low chip density. - but speed is high. - more expensive and consumes more power than the dynamic memory. SRAM included in the microprocessor chip is known as cache stores most recently used instructions or data from the slower maim memory. It can also be provided outside the processor to improve the speed of system.

WL VCC T2 Q T5 T1 T3
WL Word line BL Bit line

T4 Q T6 BL

BL

A Six Transistor CMOS SRAM Cell

Dynamic RAM (DRAM): - made up of MOS transistors. - it stores the bit as a charge.
Row (W ord line) Advantages: high density, low power consumption and low cost. Disadvantage is that the charge (bit information) leaks, therefore additional memory refreshing circuit is required. The use of DRAM is economical if the size of memory is at least 8K.

Column (bit line)

 In recent years the speed of processor has increased of about 1000MHz, so low speed DRAM is not a appropriate choice.
advancement in DRAM technology leads to high speed memory chips like EDO (Extended Data Out DRAM) SDRAM (synchronous DRAM) and RDRAM (Rambus DRAM)

Read Only Memory (ROM)

It is non-volatile memory. i.e it retains the data even if power supply is turned off. ROM is used for permanent storage of data. It is used to store look up tables, microprocessor instruction set, microcomputer system firmware etc. It is also used in encoders, sequence generators, waveform generators and in BIOS (This is the section in computers where DOS and other commands are stored).

Types of ROM
Masked ROM Programmable Read Only Memory (PROM) Erasable Programmable Read Only Memory (EPROM) Electrically Erasable (Alterable) Programmable Read Only Memory (EEPROM or EAPROM)

Masked ROM
Masked ROMs are permanently recorded by masking and metallization process. It is programmed at the time of the fabrication, according to the information specified by the user. The data stored can not be altered after the fabrication. It is an expensive and specialized process, but economical for large production quantities.

Programmable Read Only Memory (PROM)

PROM can be programmed by the user with a special PROM programmer circuitry. These memory are available without any stored from the vender. The PROM programmer selectively burns the fuses according to the bit pattern to be stored. This process is known as burning the PROM. Once the data is stored in the PROM becomes permanent.

Erasable Programmable Read Only Memory (EPROM)

This type of memory is reprogrammable. i.e. it can be programmed again and again. It is referred to as erasable and programmable read only memory. This memory makes use of MOSFETs, wherein the data stored can be erased by exposing this memory to ultra violate radiations, through a quartz window available on the chip, for about 20 30 minutes. About1000 program/erase cycles. EPROMs are commonly used in program development and experimental projects.

Electrically Erasable (Alterable) Programmable Read Only Memory (EEPROM or EAPROM)

This memory is functionally similar to EPROM; except that the stored information can be electrically erased. This chip allows selective erasing at the register level rather than erasing the entire information. For erasing the contents of this memory an electrical signal of proper polarity and amplitude is applied. The EAPROM has a special chip erase mode by which entire memory can be erased in 10 ms. This is quit small as compared to time required to erase EPROM

Flash memory :
Applications: Your computer BIOS (Basic Input Output System) Memory Cards Mp3 players Modems Video game cards Digital cellular phones Digital cameras

Dr. Fujio Masuoka

 Since the early 1990s, flash EPROM has become a popular user-programmable memory chip, because the erase method is electrical and of high speed (one might say in a flash) hence the name Flash Memory. The major difference in the flash memory and EPROM is its erasure method. EPROM is erasing by optical (UV radiation) method. Entire contents of Flash memory are erased when it is exposed to electrical signal; in contrast the contents of EEPROM are erased in desired section or bytes.
Although resent advancement in the flash memory design erasure can be done block by block, unlike EEPROM, flash memory dont have a byte erasure option.

The structure of NAND flash cell. The black lines represent current paths with or without wires.

The induction of an electric field (blue outline) along the lines excites electrons and forces them through the oxide layer to become trapped in the floating gate.

Flash memory employs blocks composed of thousands of NAND cells. Each block uses a common word and bit line.

Applications: Your computer BIOS Memory Cards Mp3 players Modems Video game cards Digital cellular phones Digital cameras

Charge Coupled Device Memory

It is an array of MOS capacitors operating as a dynamic shift register. CCDs are simple, versatile and low cost devices and can be used wherever a serial accessed memory is required. The charge-coupled device was invented in 1969 at AT&T Bell Labs by Willard Boyle and George E. Smith. The lab was working on semiconductor bubble memory. The operation of CCDs involves the following steps:
Conversion of digital data into charge. Transfer of charge through various stages in sequential manner, and Conversion of charge in to digital data at the output.

 During each charge transfer step, a small amount charge is lost. Also, due to thermal effects, undesirable charge may be produced which is known as dark current. To avoid these effects, the charge is recirculated around the shift register for refreshing.

Basic Concept of CCD

+V1 V2 = 0 V3 = 0 V4 = 0 G1
Depletion Region

G2

G3

G4

Metal Electrodes
SiO 2 Layer

p - ty pe substrate

1 = +V

2 = 3 = 4 = 0

G1
Charge Inj ected

G2

G3

G4

Metal Electrodes
SiO 2 Layer

p - ty pe substrate

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0
3 = 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0
4 = 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0
3 = 0 4 = 0

t1
Gate (metal electrode) Inject Charges

t1

1 = +V 2 = 0

1 = +V 2 = 0

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0
4 = 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0
1 = V

3 0 1 1 1 1 1 1 0 0
2 =0

4 0 0 0 0 0 0 1 1 0
3 = V 4 = 0

t2
1 = V
Gate (metal electrode)

t1
2 =0

3 = V

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t3
1 = V
Gate (metal electrode)

t1

2 = V

3 = V

4 = 0

1 = V

2 = V

3 = V

4 = 0

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t4
1 = 0
Gate (metal electrode)

t1

2 = V

3 = V

4 = 0

1 = 0

2 =V

3 =V

4 = 0

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t5
1 = 0
Gate (metal electrode)

t1

2 =0

3 = V

4 = 0

1 = 0

2 =0

3 = V

4 = 0

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t6
1 = V
Gate (metal electrode)

t1

2 =0

3 = V

4 = 0

1 = V

2 =0

3 = V

4 = 0

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t7
1 = V
Gate (metal electrode)

t1

2 =0

3 = V

4 = V

1 = V

2 =0

3 = V

4 = V

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t8
1 = V
Gate (metal electrode)

t1

2 =0

3 = 0

4 = V

1 = V

2 =0

3 = 0

4 = V

SiO2 layer

1 t1 t2 t3 t4 t5 t6 t7 t8 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

1 1 1 1 0 0 1 1 1 1

2 0 0 1 1 0 0 0 0 0

3 0 1 1 1 1 1 1 0 0

4 0 0 0 0 0 0 1 1 0

t1
1 = V
Gate (metal electrode)

t1

2 =0

3 = 0

4 = V

1 = V

2 =0

3 = 0

4 = 0

SiO2 layer

t1

t2

t3

t4

t5

A Practical CCD Memory Device

256 - bi t recircul ati ng regi ster No. 0 256 - bi t recircul ati ng regi ster No. 1

Data out Buffer

Data output

1 Out of 64 Decoder
256 - bi t recircul ati ng regi ster No. 62 256 - bi t recircul ati ng regi ster No. 63

Data in Buffer

Data i nput wri te enabl e

Address input buffer

A0 A1 A2 Address A3 inputs A4 A5

Four phase cl ock inputs

Block Organisation of Intel 2416 CCD Mem ory

Basic organisation of Intel 2416 CCD memory it is a 16384 X 1 bit serial memory organised as 64 independent recalculating shift registers of 256 bits each. Any one of the 64 register can be accessed by applying the appropriate 6-bit code at the address input. The data in the shift registers is simultaneously shifted by using the 4- phase clock signals 1 through 4. After a shift cycle, each of the 64 register can be selected for an input/output operation by applying the appropriate 6-bit code.

 When addressed, one bit is written into or read from the memory. If the address input is fixed, then as shifting progresses, the bit position in the addressed register will be presented serially for reading or writing. The output is open-drain which allows wired-OR connection. During the interval between shifts, we can have access to bit from each of the registers by changing the address. The 64 bits, which can be accessed by changing address, are available on a random access basis. The 256 bits in a single register are available only in the serial mode.

 In a serial mode operation, access to a desired bit may require no shift or it may require up to a maximum of 256 shifts. On an average, 256/2 = 128 shifts are required for accessing a bit. This access time in serial operation is known as latency or latency time.