8259a Programmable Interrupt Controller 2
8259a Programmable Interrupt Controller 2
INTERRUPT CONTROLLER
NEED FOR 8259A
• 8085 Processor has only 5 hardware interrupts.
• Consider an application where a number of I/O devices
connected with CPU desire to transfer data using
interrupt driven data transfer mode. In this process more
number of interrupt pins are required.
• In these multiple interrupt systems the processor will
have to take care of priorities.
8259A PIC
• Able to handle a number of interrupts at a
time.
• Takes care of a number of simultaneously
appearing interrupt requests along with
their types and priorities.
• Compatible with 8-bit as well as 16-bit
processors.
8259A PIC- FEATURES
• Manage 8 interrupts according to the
instructions written into the control registers.
• Vector an interrupt request anywhere in the
memory map. However all the 8 interrupts are
spaced at an interval of four to eight locations.
• Resolve 8 levels of interrupt priorities in variety
of modes.
• Mask each interrupt request individually.
• Read the status of pending interrupts, in-service
interrupts and masked interrupts.
8259A PIC- FEATURES
• Accept either the level triggered or the edge
triggered interrupt request.
• Be expanded to 64 priority levels by cascading
additional 8259As.
• Compatible with 8-bit as well as 16-bit
processors.
8259A PIC- BLOCK DIAGRAM
It includes 8 blocks.
• Control logic
• Read/Write logic
• Data bus buffer
• Three registers (IRR,ISR and IMR)
• Priority resolver
• Cascade Buffer
8259A PIC- BLOCK DIAGRAM
8259A PIC- PIN DIGRAM
8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION
This section consists of
• IRR (Interrupt
IRR
Request Register) • 8 interrupt inputs set
corresponding bits of
• ISR (In-Service
IRR
Register)
• Used to store the
• Priority Resolver
information about the
• IMR (Interrupt Mask interrupt inputs
Register) requesting service.
• Control logic block
8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION
ISR PRIORITY RESOLVER
IMR
• This register can be programmed by an OCW to
store the bits which mask specific interrupts.
• IMR operates on the IRR.
• An interrupt which is masked by software (By
programming the IMR) will not be recognized
and serviced even if it sets corresponding bits in
the IRR.
8259A PIC- INTERRUPTS AND CONTROL
LOGIC SECTION
CONTROL LOGIC
• Has two pins:
INT (Interrupt) Output
( Interrupt Acknowledge) Input
• INT Connected to Interrupt pin of MPU.
When interrupt occurs this pin goes high.
8259A PIC- BLOCK DIAGRAM
DATA BUS BUFFER
• 8 bit
• Bidirectional
• Tri-state Buffer used to Interface the 8259 to the
system data bus.
• Control words, Status words and vectoring data
are all passed through the data bus buffer.
8259A PIC- READ/WRITE CONTROL LOGIC
SECTION
• Contains ICW and OCW registers which are programmed
by the CPU to set up the 8259 and to operate it in various
modes.
• Also accepts read command from CPU to permit the CPU
to read status words.
• Chip Select Active Low input
Used to select the Device.
• Read Active Low input
Used by CPU to read the status of
ISR,IRR,IMR or the Interrupt level.
• Write Active Low input
Used to write OCW and ICW onto the 8259.
*ICW Initialization Control Word
8259A PIC- CASCADE BUFFER/
COMPARATOR
• Generates control signals for cascade operation.
• Also generates buffer enable signals.
• 8259 cascaded with other 8259s
Interrupt handling capacity to 64 levels
Former is called master and latter is slave.
• 8259 can be set up as master or slave by
pin in non-buffered mode or by software if it is to
be operated in the buffered mode of operation.
8259A PIC- CASCADE BUFFER/
COMPARATOR
CAS 0-2
• For master 8259 these pins are outputs and for slaves these are
inputs.
• When 8259 is a master the CALL op-code is generated by master in
response to the first Interrupt acknowledge.
• The vectoring address must be released by slave 8259.
• The master puts out the identification code to select one of the slave
from 8 slaves through these pins.
• The slave accepts these three signals as inputs and compare the
code put out by the master with the codes assigned to them during
initialization.
• The slave thus selected puts out the address of ISR during second
and third interrupt acknowledge pulses from the CPU.
8259A PIC- CASCADE BUFFER/
COMPARATOR
Slave Program/ Enable Buffer:
• Used to specify whether 8259 is to act as a
master or a slave
High Master
Low Slave
• In Non-Buffered Mode, this pin is used to specify
whether 8259 is to act as a master or a slave.
• In Buffered mode this pin is used as an output to
enable the data bus buffer of the system.
8259A PIC- INTERRUPT OPERATION
• To implement interrupt, the interrupt Enable FF must be
enabled by writing EI instruction.
• 8259A should be initialized by writing control words in
the control register.
• 8259 requires two types of control words:
ICW Used to set up proper conditions
and specify RST vector address.
OCW Used to perform functions such as
masking interrupts, setting up status
read operations etc.
• After 8259A is initialized, the following sequence of
events occurs when one or more interrupt request lines
go high.
8259A PIC- INTERRUPT OPERATION
BUFFERED MODE
CASCADE MODE
8259A- OPERATING MODES
END OF INTERRUPT (EOI):
• After the completion of an interrupt service, the
corresponding ISR bits needs to be reset to update the
information in the ISR. This is called EOI command.
It can be issued in three formats:
NON SPECIFIC EOI COMMAND:
• When this command is sent to 8259A, it resets the
highest priority ISR bit.
SPECIFIC EOI COMMAND:
• This command specifies which ISR bit is to reset.
8259A- OPERATING MODES
AUTOMATIC EOI:
• In this mode, no command is necessary.
• During the third interrupt acknowledge
cycle, the ISR bit is reset.
• DRAWBACK: The ISR does not have
information about which ISR is being
serviced. Thus, any IR can interrupt the
service routine, irrespective of its priority, if
the interrupt enable FF is set.
ADDITIONAL FEATURES OF THE 8259A
INTERRUPT TRIGGERING:
• 8259A can accept an interrupt request with either the
edge triggered or level triggered mode.
• Mode is determined by initialization instructions.
INTERRUPT STATUS:
• The status of the three interrupt registers (IRR, ISR and
IMR) can be read, and this status information can be
used to make the interrupt process versatile.
POLL METHOD:
• 8259A can be set up to function in polled environment.
• MPU polls the 8259A rather than each peripheral.