Memory Interfacing

Memory Interfacing
Mr. S. Sandeep Assistant Professor, Department of E.C.E GVPTSOE
Objectives
Upon completion you will be able to:
How to interface a memory device with p How to access memory in READ or WRITE Describe memory structure with all its type: RAM, EPROM etc Memory requirements Address Decoding types Interfacing examples
Terminology and Operations

Memory are made up of (registers). Each register consists of one storage location. Each location consists of an address. The number of storage locations from few hundreds to several mega or giga locations. The total number of memory storage is called memory capacity and measured in Bytes. Each register consists of storage element (FF, capacitor for semiconductor) . A storage element is called cell. The data could be read from or written to memory .
Memory Structure and its requirements

As
mentioned earlier, read/write memories consist of an array of registers, in which each register has unique address. size of the memory is N x M as shown below where N is the number of registers and M is the word length, in number of bits .
The
Logic Diagram of RAM
Logic Diagram of EPROM
Example
1: If memory is having 12 address lines and 8 data lines, then Number of registers/ memory locations (capacity) = 2N= 212= 4096. Word length = M bit = 8 bit Example 2: If memory has 8192 memory locations, then it has 13 address lines. (How?)
The following table summarizes capacity with address

Memory Capacity 1k = 1024 memory locations 2k = 2048 memory locations 4k = 4096 memory locations 8k = 8192 memory locations 16k = 16384 memory locations 32k = 32768 memory locations 64k = 65536 memory locations Address lines Required 10 11 12 13 14 15 16
Basic Memory Interfacing with 8085

For interfacing memory devices to p 8085, keep the following points in your mind:

p 8085 can access 64KB memory since address bus is 16-bit. Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as data memory. The capacity of program memory and data memory depends on the application. It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and multiple RAMs as per the requirement of application.
Supposing if We have to implement 32 KB of program memory and 4KB EPROMs are available. In this case we can connect 8 EPROMs in parallel. We can place EPROM/RAM anywhere in full 64 KB address space. But program memory (EPROM) should be located from address 0000 H. It is not always necessary to locate EPROM and RAM in consecutive memory address.

The memory interfacing requires to: Select the chip Identify the register Enable the appropriate buffer.
p system includes memory and I/O devices. It is important to note that p can communicate (read/write) with only one device at a time, so address decoding needed.
Address Decoding techniques

There
are two main techniques:
Absolute decoding/ Full Decoding. Linear decoding / Partial Decoding .
Absolute Decoding
All
the higher address lines are decoded to select the memory chip, and the memory chip is selected only for the specified logic level on these high-order address, no other logic levels can select the chip. addressing technique is normally used in large memory systems
This
Absolute Decoding Technique
Absolute Decoding Technique
Linear Decoding
In small systems, h/w for the decoding logic can be eliminated by using individual highorder address lines to select memory chips. This is referred to as linear decoding. The figure below shows the addressing of RAM with linear decoding technique. This technique is also called partial decoding. It reduces the cost of the decoding, but it has a drawback of multiple address (shadow addresses)
Linear decoding Technique
Linear decoding Technique
EXAMPLE 1
Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor.

The memory capacity is 64 Kbytes, that is , 2^n = 64 x 1000 bytes where n = address lines. Hence, n = 16. ( n = log2 64*1000). In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory. The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground). Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM. The range of address for EPROM is 0000H to FFFFH.
Fig - Interfacing 64Kb EPROM with 8085
EXAMPLE 2
Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM. Interface the EPROM and RAM with 8085 processor.

Implement 32kb memory capacity of EPROM using single IC 27256. 32kb RAM capacity is implemented using single IC 62256. The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are connected to 15 address pins of both EPROM and RAM. The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15 is 0, it select EPROM. Inverter is used for selecting the memory. The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively. The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH to FFFFH.
Fig - Interfacing 32Kb EPROM and 32Kb RAM with 8085
EXAMPLE 3
Consider a system in which 32kb memory space is implemented using four number of 8kb memory. Interface the EPROM and RAM with 8085 processor.

The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. Each 8kb memory requires 13 address lines and so the address lines A0A12 of the processor are connected to 13 address pins of all the memory. The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select signals. These four chip select signals can be used to select one of the four memory IC at any one time. The address line A15 is used as enable for decoder. The simplified schematic memory organization is shown.
Fig - Interfacing 16Kb EPROM and 16Kb RAM with 8085
The address allotted to each memory IC is shown in following table.
EXAMPLE 4
Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.

The total memory capacity is 64Kb. So, let 4 numbers of 8Kb EPROM and 4 numbers of 8Kb RAM. Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the processor are connected to 13address pins of all the memory ICs. The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate eight chip select signals. These eight chip select signals can be used to select one of the eight memories at any one time. The memory interfacing is shown in following figure.
Fig - Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085
The address allocation for Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085 is:

Memory Interfacing

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How are memories interfaced with microprocessors?

How are memories interfaced with microprocessors?

What are the different types of memories discussed?

What are the different types of memories discussed?

Memory Interfacing

Mr. S. Sandeep Assistant Professor, Department of E.C.E GVPTSOE

Terminology and Operations

Memory Structure and its requirements

Logic Diagram of RAM

Logic Diagram of EPROM

The following table summarizes capacity with address

Basic Memory Interfacing with 8085

Address Decoding techniques

are two main techniques:

Absolute decoding/ Full Decoding. Linear decoding / Partial Decoding .

Absolute Decoding Technique

Absolute Decoding Technique

Linear decoding Technique

Linear decoding Technique

Fig - Interfacing 64Kb EPROM with 8085

Fig - Interfacing 32Kb EPROM and 32Kb RAM with 8085

Fig - Interfacing 16Kb EPROM and 16Kb RAM with 8085

The address allotted to each memory IC is shown in following table.

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