EE 587 SoC Design & Test

Partha Pande School of EECS Washington State University [email protected]

Test Methodologies, and Yield

Reference: Essentials of Electronic Testing by Bushnell and Agrawal

Introduction
VLSI realization process Verification and test Ideal and real tests Costs of testing

VLSI Realization Process

Customers need
Determine requirements

Write specifications
Design synthesis and Verification

Test development
Fabrication Manufacturing test

Chips to customer

Definitions

Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

Verification vs. Test

Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.

Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.

Problems of Ideal Tests

Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open

problem.

Defect vs. Fault

To become a fault, the defect needs to connect two disjoint conductors or disconnect a continuous pattern

Wafer Defect Map

Faults are a percentage of defects

Same distribution with fewer points

Real Tests

Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

Testing as Filter Process

Good chips Prob(pass test) = high Prob (good) = y Fabricated chips Defective chips Prob(bad) = 1- y Prob(fail test) = high Mostly bad chips Mostly good chips

Costs of Testing

Design for testability (DFT)

Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

Design for Testability (DFT)

DFT refers to hardware design styles or added hardware that reduces test generation complexity.
Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. Logic bus Logic PO PI block A block B Test input

Test output

Present and Future*

1997 -2001 2003 - 2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10 Transistors/sq. cm 4 - 10M 18 - 39M

Pin count Clock rate (MHz) Power (Watts)

100 - 900 200 - 730 1.2 - 61

160 - 1475 530 - 1100 2 - 96

* SIA Roadmap, IEEE Spectrum, July 1999

Cost of Manufacturing Testing in 2000AD

0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

Roles of Testing

Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

Yield Analysis & Product Quality

Yield and manufacturing cost Clustered defect yield formula Yield improvement

Defect level
Test data analysis Example: SEMATECH chip Summary

VLSI Chip Yield

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip:

Cost of fabricating and testing a wafer -------------------------------------------------------------------Yield x Number of chip sites on the wafer

Clustered VLSI Defects

Good chips

Faulty chips

Defects Wafer
Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

Yield Parameters

Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter (a) Negative binomial distribution of defects, p (x ) = Prob (number of defects on a chip = x )

(Ad /a) x = ------------- . ---------------------x ! G (a) (1+Ad /a) a+x where G is the gamma function a =0, p (x ) is a delta function (max. clustering) a = , p (x ) is Poisson distr. (no clustering)

G (a+x )

Yield Equation
Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / a ) - a
Example: Ad = 1.0, a = 0.5, Y = 0.58 Unclustered defects: a = Example: Ad = 1.0, a =

, Y = e - Ad
, Y = 0.37

too pessimistic !

Defect Level or Reject Ratio

Defect level (DL) is the ratio of faulty

chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

Determination of DL

From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

Modified Yield Equation

Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, b Stuck-at fault coverage, T The modified yield equation:

Y (T ) = (1 + TAf / b) - b
Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips,

Y = Y (1) = (1 + Af / b) - b

Defect Level
DL (T ) = -------------------Y (T )
( b + TAf ) = 1 - -------------------b

Y (T ) - Y (1)

( b + Af ) Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, b is the fault clustering parameter. Af and b are determined by test data analysis.

Test Coverage from Fault Simulator

Stuck-at fault coverage

Vector number

Measured Chip Fallout

Measured chip fallout

Vector number

Model Fitting
Chip fallout and computed 1-Y (T )

Chip fallout vs. fault coverage

Y (1) = 0.7623

Measured chip fallout

Y (T ) for Af = 2.1 and b = 0.083

Stuck-at fault coverage, T

Computed DL
237,700 ppm (Y = 76.23%)

Defect level in ppm

Stuck-at fault coverage (%)

Summary

VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (a) Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99%