Scribd
Upload
80 views24 pages

ECE2030 Introduction To Computer Engineering Lecture 3: Switches and CMOS

path exists when the Switch Control is closed If (Open) OUTPUT = unknown ; Switch is open (OFF) Else OUTPUT = INPUT ; Switch is closed (ON)

Uploaded by

Azman Mat Hussin
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
80 views24 pages

ECE2030 Introduction To Computer Engineering Lecture 3: Switches and CMOS

path exists when the Switch Control is closed If (Open) OUTPUT = unknown ; Switch is open (OFF) Else OUTPUT = INPUT ; Switch is closed (ON)

Uploaded by

Azman Mat Hussin
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 24

ECE2030 Introduction to Computer Engineering Lecture 3: Switches and CMOS

Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

Basic Switch
A path exists when the Switch Control is closed
If (Open) OUTPUT = unknown ; Switch is open (OFF) Else OUTPUT = INPUT ; Switch is closed (ON)

Switch Control INPUT OUTPUT

The Analogy of A Transistor


Switch Control (Gate) INPUT OUTPUT

Cross Section
An N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET)

Transistor Characteristics
Cut-off Region
Vgs Vt 0 No current (Ids) between drain and source

Linear (or Ohmic) Region


0 < Vds < Vgs Vt Ids is a function of Vgs and Vds Ids = *[(Vgs-Vt)*Vds Vds*Vds/2]
Drain Gate Vgs Ids Source Vds

Saturation Region
0 < Vgs Vt < Vds Ids is independent of Vds Ids = (/2)*(Vgs-Vt)2 = process factor * (W/L)

N-type MOS Transistor

Vt : Threshold voltage, a function of materials, doping, insulator thickness, etc.


4
4

Transistor Characteristics

Switches in Series
INPUT Truth Table S1

S1 OFF OFF

S2 OFF ON OFF ON

PATH?

S2

ON ON
OUTPUT

Switches in Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 OFF OFF

S2 OFF ON OFF ON
What Function ??

PATH? NO NO NO YES

S2

ON ON
OUTPUT

Switches in Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 0

S2 0

PATH? 0

S2

OUTPUT

Function = ??

Switches in Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 0 0

S2 0 1

PATH? 0 0

S2

OUTPUT

Function = ??

Switches in Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 0 0

S2 0 1 0

PATH? 0 0 0

S2

OUTPUT

Function = ??

10

10

Switches in Series
INPUT Truth Table (OFF/ON=0/1) S1

S1 0 0

S2 0 1 0 1

PATH? 0 0 0 1

S2

1 1
OUTPUT

Function = Logic AND

11

11

Switches in Parallel
INPUT Truth Table

S1 OFF
S1 S2

S2 OFF ON OFF ON

PATH? NO YES YES YES

OFF ON ON

OUTPUT

12

12

Switches in Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0

PATH? 0

OUTPUT

Function =??

13

13

Switches in Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0 1

PATH? 0 1

OUTPUT

Function =??

14

14

Switches in Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0 1 0

PATH? 0 1 1

0 1

OUTPUT

Function =??

15

15

Switches in Parallel
INPUT Truth Table

S1 0
S1 S2

S2 0 1 0 1

PATH? 0 1 1 1

0 1 1

OUTPUT

Function = Logic OR

16

16

CMOS Transistor
Complementary MOS
Source Gate Drain pMOS

P-channel MOS (pMOS) N-channel MOS (nMOS)

pMOS
P-type source and drain diffusions N substrate Mobility by holes

Drain Gate Source nMOS


17

nMOS
N-type source and drain diffusions P substrate Mobility by electrons
17

Pass Transistor using NMOS


Gate=Vdd Vin=Vdd I Load Capacitor Vgs

Vout

Assume capacitor (CL) is initially discharged Gate=1, Vin=1


CL begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt) Signal is degraded

Ground
Gate=Vdd Vin=0 I Load Capacitor Vgs

Gate=1, Vin=0
Vout=Vdd

CL begins to discharge toward 0


18

18

Ground

Transmission Degradation using Pass Transistor


Vdd (1) Vdd Vdd Vdd - Vt Vdd - 2Vt

Vdd

Vdd
Vout = Vdd- N*Vt Still 1??

19

19

CMOS Signal Transfer Property


Source Gate Drain pMOS

Gate
0

Path
Closed
Transmits 1 well Transmits 0 poorly

Open

Drain Gate Source nMOS


20

Gate 0 1

Path Open Closed


Transmits 0 well Transmits 1 poorly

20

CMOS Transmission Gate


Transmit signal from INPUT to OUTPUT when Gate is closed

Gate (complementary of Gate)

Gate
Source Drain

pMOS OFF ON

nMOS OFF ON

OUTPUT Z INPUT

INPUT

OUTPUT

0 1

Gate

Z : High-Impedance State, consider the terminal is floating

21

21

High Impedance
When a path exists
Impedance is low to allow ample flow of current
Gate=1 Source Closed Drain << 10K

When no path
Impedance is high allowing almost no current flow between two terminals
Gate=0 Source Open Drain >> 100M

22

22

Transmission Gates
Transmit Logic 0 Gate = 0 Transmit Logic 1 Gate = 0

Gate = 1

Gate = 1

23

23

Transmission Gate Symbol

Gate

Gate OUTPUT

INPUT

INPUT

OUTPUT

Gate

Gate

24

24

You might also like