Chapter 11

Operational Amplifiers and Applications

Chapter Goals
Understand the magic of negative feedback and the
characteristics of ideal op amps.
Understand the conditions for non-ideal op amp behavior so
they can be avoided in circuit design.
Demonstrate circuit analysis techniques for ideal op amps.
Characterize inverting, non-inverting, summing and
instrumentation amplifiers, voltage follower and first order
filters.
Learn the factors involved in circuit design using op amps.
Find the gain characteristics of cascaded amplifiers.
Special Applications: The inverted ladder DAC and successive
approximation ADC
Differential Amplifier Model: Basic
Represented by:
A = open-circuit voltage gain
v
id
= (v
+
-v
-
) = differential input signal
voltage
aR
id
= amplifier input resistance
R
o
= mplifier output resistance
developed at the amplifier output is in
phase with the voltage applied at the +
input (non-inverting) terminal and 180
out of phase with that applied at the -
input (inverting) terminal. The signal
LM741 Operational Amplifier: Circuit
Architecture
Current Mirrors
Ideal Operational Amplifier
The ideal op amp is a special case of the ideal differential amplifier
with infinite gain, infinite R
id
and zero R
o
.

and

If A is infinite, v
id
is zero for any finite output voltage.
Infinite input resistance R
id
forces input currents i
+
and i
-
to be zero.
The ideal op amp operates with the following assumptions:
It has infinite common-mode rejection, power supply rejection, open-
loop bandwidth, output voltage range, output current capability and
slew rate
It also has zero output resistance, input-bias currents, input-offset
current, and input-offset voltage.
A
o
v
id
v =
0
id
v
lim
=
A
The Inverting Amplifier: Configuration
The positive input is grounded.
A feedback network composed of resistors R
1
and R
2
is connected
between the inverting input, signal source and amplifier output node,
respectively.
Inverting Amplifier:Voltage Gain
The negative voltage gain
implies that there is a 180
0
phase
shift between both dc and
sinusoidal input and output
signals.
The gain magnitude can be
greater than 1 if R
2
> R
1

The gain magnitude can be less
than 1 if R
1
> R
2

The inverting input of the op
amp is at ground potential
(although it is not connected
directly to ground) and is said to
be at virtual ground.
0
o
v
2 2
i
1
i
s
v = R R
s
1
s
v
s
i
R
=
But i
s
= i
2
and v
-
= 0 (since v
id
= v
+
- v
-
= 0)
and
1
2
s
v
o
v
R
R
v
A = =
Inverting Amplifier: Input and Output
Resistances


R
in
=
v
s
i
s
=R
1
since v

=0
R
out
is found by applying a test current
(or voltage) source to the amplifier
output and determining the voltage (or
current) after turning off all
independent sources. Hence, v
s
= 0
1 1
i
2 2
i
x
v R R + =
But i
1
=i
2
)
1 2
(
1
i
x
v R R + =
Since v
-
= 0, i
1
=0. Therefore v
x
= 0
irrespective of the value of i
x
.
0 =
out
R
Inverting Amplifier: Example
Problem: Design an inverting amplifier
Given Data: A
v
= 20 dB, R
in
= 20kO,
Assumptions: Ideal op amp
Analysis: Input resistance is controlled by R
1
and voltage gain is set
by R
2
/ R
1
.
and A
v
= -100

A minus sign is added since the amplifier is inverting.


A
v
dB
|
\

|
.
| =20log
10
A
v
|
\

|
.
|
, A
v
=10
40dB/20dB
=100
O = = k 20
1 in
R R

A
v
=
R
2
R
1
R
2
=100R
1
=2MO
The Non-inverting Amplifier: Configuration
The input signal is applied to the non-inverting input terminal.
A portion of the output signal is fed back to the negative input
terminal.
Analysis is done by relating the voltage at v
1
to input voltage v
s
and
output voltage v
o
.

Non-inverting Amplifier: Voltage Gain,
Input Resistance and Output Resistance
Since i
-
=0 and

But v
id
=0





Since i
+
=0
2 1
1
o
v
1
v
R R
R
+
=
1
v
id
v
s
v =
1
v
s
v =
1
2
1
1
2 1
s
v
o
v
1
2 1
s
v
o
v
R
R
R
R R
v
A
R
R R
+ =
+
= =
+
=
=
+
=
i
s
v
in
R
R
out
is found by applying a test current source to the amplifier output
after setting v
s
= 0. It is identical to the output resistance of the inverting
amplifier i.e. R
out
= 0.
Non-inverting Amplifier: Example
Problem: Determine the output voltage and current for the given non-
inverting amplifier.
Given Data: R
1
= 3kO, R
2
= 43kO, v
s
= +0.1 V
Assumptions: Ideal op amp
Analysis:



Since i
-
=0,


A
v
=1+
R
2
R
1
=1+
43kO
3kO
=15.3
v
o
= A
v
v
s
=(15.3)(0.1V)=1.53V
A 3 . 33
k 3 k 43
V 53 . 1
1 2
o
v
o
i =
O + O
=
+
=
R R
Finite Open-loop Gain and Gain Error
2 1
1
o
v
o
v
2 1
1
1
v
R R
R
R R
R
+
=
=
+
=
|
|
is called the
feedback factor.
|
|
A
A
v
A
A A A
+
= =
= = =
1
s
v
o
v
)
o
v
s
v ( )
1
v
s
v (
id
v
o
v
A| is called loop gain.
For A| >>1,


A
v
~
1
|
=1+
R
2
R
1
This is the ideal voltage gain of
the amplifier. If A| is not >>1,
there will be Gain Error.
Gain Error
Gain Error is given by
GE = (ideal gain) - (actual gain)
For the non-inverting amplifier,


Gain error is also expressed as a fractional or percentage
error.
) 1 (
1
1
1
| | | | A A
A
GE
+
=
+
=


FGE=
1
|

A
1+A|
1
|
=
1
1+A|
~
1
A|
PGE~
1
A|
100%
Gain Error: Example
Problem: Find ideal and actual gain and gain error in percent
Given data: Closed-loop gain of 100,000, open-loop gain of
1,000,000.
Approach: The amplifier is designed to give ideal gain and deviations
from the ideal case have to be determined. Hence,
.
Note: R
1
and R
2
arent designed to compensate for the finite open-loop
gain of the amplifier.
Analysis:


|=
1
10
5


A
v
=
A
1+A|
=
10
6
1+
10
6
10
5
=9.09x10
4
PGE=
10
5
9.09x10
4
10
5
100%=9.09%
Output Voltage and Current Limits
Practical op amps have limited
output voltage and current ranges.
Voltage: Usually limited to a few
volts less than power supply span.
Current: Limited by additional
circuits (to limit power dissipation
or protect against accidental short
circuits).
The current limit is frequently
specified in terms of the minimum
load resistance that the amplifier
can drive with a given output
voltage swing. Eg:



i
o
=
5V
500O
=10mA
)
2 1
(
o
v
1 2
o
v
o
v
F
i
L
i
o
i
R R
L
R
EQ
R
EQ
R R R
L
R
+ =
=
+
+ = + =
For the inverting amplifier,
2
R
L
R
EQ
R =
Example PSpice Simulations of
Non-inverting Amplifier Circuits
The Unity-gain Amplifier or Buffer
This is a special case of the non-inverting amplifier, which is also
called a voltage follower, with infinite R
1
and zero R
2
. Hence A
v
= 1.
It provides an excellent impedance-level transformation while
maintaining the signal voltage level.
The ideal buffer does not require any input current and can drive any
desired load resistance without loss of signal voltage.
Such a buffer is used in many sensor and data acquisition system
applications.
The Summing Amplifier
Scale factors for the 2 inputs
can be independently adjusted
by the proper choice of R
2
and
R
1
.
Any number of inputs can be
connected to a summing
junction through extra
resistors.
This circuit can be used as a
simple digital-to-analog
converter. This will be
illustrated in more detail, later.
1
1
v
1
i
R
=
2
2
v
2
i
R
=
3
o
v
3
i
R
=
Since the negative amplifier
input is at virtual ground,

Since i
-
=0, i
3
= i
1
+ i
2
,


v
o
=
R
3
R
1
v
1

R
3
R
2
v
2
The Difference Amplifier
This circuit is also called a
differential amplifier, since it
amplifies the difference between
the input signals.
R
in2
is series combination of R
1

and R
2
because i
+
is zero.
For v
2
=0, R
in1
= R
1
, as the circuit
reduces to an inverting amplifier.
For general case, i
1
is a function
of both v
1
and v
2
.
1
v
1
2
-
v
1
2 1
)
-
v
1
v (
1
2
-
v
2 1
i
-
v
2 2
i
-
v
o
v
R
R
R
R R
R
R
R R

+
=
= =
|
|
|
|
|
.
|

\
|
=


v
+
=
R
2
R
1
+R
2
v
2
Also,
Since v
-
= v
+
)
2
v
1
(v
1
2
v =
R
R
o
For R
2
= R
1

)
2
v
1
(v v =
o
Difference Amplifier: Example
Problem: Determine v
o

Given Data: R
1
= 10kO, R
2
=100kO, v
1
=5 V, v
2
=3 V
Assumptions: Ideal op amp. Hence, v
-
= v
+
and i
-
= i
+
= 0.
Analysis: Using dc values,


A
dm
=
R
2
R
1
=
100kO
10kO
=10
V
o
= A
dm
V
1
V
2
|
\


|
.
|
|
=10(53)
V
o
=20.0 V
Here A
dm
is called the differential mode voltage gain of the difference amplifier.
Finite Common-Mode Rejection Ratio
(CMRR)
A(or A
dm
) = differential-mode gain
A
cm
= common-mode gain
v
id
= differential-mode input voltage
v
ic
= common-mode input voltage
A real amplifier responds to signal
common to both inputs, called the
common-mode input voltage (v
ic
).
In general,


v
o
= A
dm
v
id
+
A
cm
v
ic
A
dm
|
\




|
.
|
|
|
|
= A
dm
v
id
+
v
ic
CMRR
|
\



|
.
|
|
|
CMRR=
A
dm
A
cm

and CMRR(dB)=20log
10
(CMRR)
An ideal amplifier has A
cm
= 0, but for a
real amplifier,
2
1
id
v
ic
v v + =
2
2
id
v
ic
v v =

v
o
= A
dm
(v
1
v
2
)+A
cm
v
1
+v
2
2
|
\



|
.
|
|
|
v
o
= A
dm
(v
id
)+A
cm
(v
ic
)
Finite Common-Mode Rejection Ratio:
Example
Problem: Find output voltage error introduced by finite CMRR.
Given Data: A
dm
= 2500, CMRR = 80 dB, v
1
= 5.001 V, v
2
= 4.999 V
Assumptions: Op amp is ideal, except for CMRR. Here, a CMRR in dB
of 80 dB corresponds to a CMRR of 10
4
.
Analysis:







The output error introduced by finite CMRR is 25% of the expected ideal
output.



v
id
=5.001V4.999V
v
ic
=
5.001V+4.999V
2
=5.000V
v
o
= A
dm
v
id
+
v
ic
CMRR
|
\


|
.
|
|
=2500 0.002+
5.000
10
4
|
\


|
.
|
|
V=6.25V
In the "ideal" case, v
o
= A
dm
v
id
=5.00 V


% output error=
6.255.00
5.00
100%=25%
uA741 CMRR Test: Differential Gain
Differential Gain A
dm
= 5 V/5 mV = 1000
uA741 CMRR Test: Common Mode Gain
Common Mode Gain A
cm
= 160 mV/5 V = .032
CMRR Calculation for uA741

CMRR =
A
dm
A
cm
=
1000
.032
= 3.125x10
4
CMRR(dB) = 20log
10
CMRR
( )
= 89.9 dB
Instrumentation Amplifier
Combines 2 non-inverting amplifiers
with the difference amplifier to
provide higher gain and higher input
resistance.
)
b
v
a
(v
3
4
v =
R
R
o
b
v
2
i )
1
i(2
2
i
a
v = R R R
1
2
2
v
1
v
i
R

=
)
2
v
1
(v
1
2
1
3
4
v + =
|
|
|
|
|
.
|

\
|
R
R
R
R
o
Ideal input resistance is infinite
because input current to both op
amps is zero. The CMRR is
determined only by Op Amp 3.
NOTE
Instrumentation Amplifier: Example
Problem: Determine V
o

Given Data: R
1
= 15 kO, R
2
= 150 kO, R
3
= 15 kO, R
4
= 30 kO V
1
= 2.5 V,
V
2
= 2.25 V
Assumptions: Ideal op amp. Hence, v
-
= v
+
and i
-
= i
+
= 0.
Analysis: Using dc values,



A
dm
=
R
4
R
3
1+
R
2
R
1
|
\




|
.
|
|
|
|
=
30kO
15kO
1+
150kO
15kO
|
\


|
.
|
|
=22
V
o
= A
dm
(V
1
V
2
)=22(2.52.25)=5.50V
The Active Low-pass Filter
Use a phasor approach to gain analysis of
this inverting amplifier. Let s = je.


A
v
=
v
o
( je)
v ( je)
=
Z
2
( je)
Z
1
( je)


Z
1
je
( )
=R
1


Z
2
( je)=
R
2
1
jeC
R
2
+
1
jeC
=
R
2
jeCR
2
+1


A
v
=
R
2
R
1
1
(1+ jeCR
2
)
=
R
2
R
1
e
jt
(1+
je
e
c
)


e
c
=2tf
c
=
1
R
2
C
f
c
=
1
2tR
2
C
f
c
is called the high frequency cutoff of
the low-pass filter.
Active Low-pass Filter (continued)

At frequencies below f
c
(f
H
in the
figure),

the amplifier is an
inverting amplifier with gain set
by the ratio of resistors R
2
and
R
1
.
At frequencies above f
c
, the
amplifier response rolls off at
-20dB/decade.
Notice that cutoff frequency and
gain can be independently set.


A
v
=
R
2
R
1
e
jt
(1+
je
e
c
)
|
\







|
.
|
|
|
|
|
|
|
=
R
2
R
1
1
2
+
e
e
c
|
\




|
.
|
|
|
|
2
e
jt
e
jtan
1
(e/e
c
)
|
\






|
.
|
|
|
|
|
|
=
R
2
R
1
1+
e
e
c
|
\




|
.
|
|
|
|
2
e
j[t tan
1
(e/e
c
)]
magnitude phase
Active Low-pass Filter: Example
Problem: Design an active low-pass filter
Given Data: A
v
= 40 dB, R
in
= 5 kO, f
H
= 2 kHz
Assumptions: Ideal op amp, specified gain represents the desired low-
frequency gain.
Analysis:
Input resistance is controlled by R
1
and voltage gain is set by R
2
/ R
1
.
The cutoff frequency is then set by C.




The closest standard capacitor value of 160 pF lowers cutoff frequency
to 1.99 kHz.
100
dB 20 / dB 40
10 = =
v
A
O = = k 5
1 in
R R


A
v
=
R
2
R
1
R
2
=100R
1
=500kO


C=
1
2tf
H
R
2
=
1
2t(2kHz)(500kO)
=159pF
and
Low-pass Filter Example PSpice Simulation
Output Voltage Amplitude in dB
Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)
Cascaded Amplifiers
Connecting several amplifiers in cascade (output of one stage connected to
the input of the next) can meet design specifications not met by a single
amplifier.
Each amplifer stage is built using an op amp with parameters A, R
id
, R
o
,
called open loop parameters, that describe the op amp with no external
elements.
A
v
, R
in
, R
out
are closed loop parameters that can be used to describe each
closed-loop op amp stage with its feedback network, as well as the overall
composite (cascaded) amplifier.
Two-port Model for a 3-stage Cascade
Amplifier
Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-port
model.


v
o
=A
vA
v
s
R
inB
R
outA
+R
inB
|
\




|
.
|
|
|
|
A
vB
R
inC
R
outB
+R
inC
|
\




|
.
|
|
|
|
A
vC
vC
A
vB
A
vA
A
v
A = =
s
v
o
v
Since R
out
= 0
R
in
= R
inA
and

R
out
= R
outC
= 0
A Problem: Voltage Follower Closed
Loop Gain Error due to A and CMRR
o
v
s
v
id
v =
2
o
v
s
v
ic
v
+
=


v
o
= A v
s
v
o
( )
+
v
s
+v
o
( )
2(CMRR)
|
\



|
.
|
|
|
A
v
=
v
o
v
s
=
A1+
1
2(CMRR)
|
\



|
.
|
|
|
1+A1
1
2(CMRR)
|
\



|
.
|
|
|
The ideal gain for the voltage
follower is unity. The gain error
here is:


GE=1A
v
=
1
A
CMRR
1+A1
1
2(CMRR)
|
\



|
.
|
|
|
Since, both A and CMRR are
normally >>1,


GE~
1
A

1
CMRR
Since A ~ 10
6
and CMRR ~ 10
4
at
low to moderate frequency, the gain
error is quite small and is, in fact,
usually negligible.
Inverted R-2R Ladder DAC
A very common DAC circuit architecture with good precision.
Currents in the ladder and the reference source are independent of digital
input. This contributes to good conversion precision.
Complementary currents are available at the output of inverted ladder.
The bit switches need to have very low on-resistance to minimize
conversion errors.
Successive Approximation ADC
Binary search is used by the SAL to determine v
X
.
n-bit conversion needs n clock periods. Speed is
limited by the time taken by the DAC output to
settle within a fraction of an LSB of V
FS
, and by the
comparator to respond to input signals differing by
small amounts.
Slowly varying input signals, not changing by
more than 0.5 LSB (V
FS
/2
n+1
) during the
conversion time (T
T
= nT
C
) are acceptable.
For a sinusoidal input signal with p-p amplitude =
V
FS
,

To avoid this frequency limitation, a high speed
sample-and-hold circuit is used ahead of the
successive approximation ADC.
This is a very popular ADC with fast conversion
times, used in 8- to 16- bit converters.

f
o
s
f
c
2
n+2
(n+1)t
SAADC: Block Diagram
SAADC: Method of Operation