Introduction to Computing Systems

from bits & gates to C & beyond

Chapter 3
Digital Logic Structures
Transistors Logic gates & Boolean logic Combinational logic Storage Elements Memory

CMOS Transistors

CMOS
= Complementary Metal-Oxide Semiconductor Standard type for digital applications Two versions: P-type (positive) and N-type (negative) P and N-type transistors operate in inverse modes

P
G

N
G

Open (insulating) if gate is on = 1 Closed (conducting) if gate is off = 0

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Open (insulating) if gate is off = 0 Closed (conducting) if gate is on = 1

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Inverter Gate
2.9 v

P
in
out

In Out 0 1 1 0

When the input is on (in = high voltage), the P-type transistor is open and the Ntype is closed, so the output is off (out = low voltage).
Vice-versa: when the Input is off (in = low voltage), the output is connected to the high voltage.

N
0v

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NOR Gate
2.9 v A

P
C

N N
0v 0v
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A 0 0 1 1

B 0 1 0 1

C 1 0 0 0

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OR Gate
= a NOR gate followed by an inverter A B

A 0 0 1 1

B 0 1 0 1

C 1 0 0 0

D 0 1 1 1

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NAND & AND Gates

B
C

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

D 0 0 0 1

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Logic Gates & Symbols

Note that gates can have more than 2 inputs.

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De Morgans Law

not(A and B) = (not A) or (not B)

A and B A or B
=

not(A or B) = (not A) and (not B)

A or B A and B
=

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Representation of Logic Functions

A logic function can be represented as

a truth table a logic expression a logic circuit

Example

f a.(b.c d) a.c a.b.c a.d a.c

a b c f

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

f 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1

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Types of Logic Structures

Two types of logic structures ==> two types of logic circuits
Decision structures: can make a decision based only on the current inputs: gates belong to this category. Storage structures: permit the storage of information (as bits).

Combinational logic circuits

a combinational logic structure is constructed from decision elements only: i.e. simple gates or other combinational logic circuits. its output depends solely on its current input.

Sequential logic circuits

combine combinational circuits & storage devices - well deal with these shortly.

Three examples of combinational logic circuits

Decoder Multiplexer (MUX) Full adder
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Decoder
A B
i=0

1, iff A,B is 00

An n input decoder has 2n outputs.

Outputi is 1 iff the binary value of the n-bit input is i. At any time, exactly one output is 1, all others are 0.

i=1

1, iff A,B is 01

i=2

1, iff A,B is 10

i=3

1, iff A,B is 11

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Multiplexer (MUX)
A B C D S0 S1 In general, a MUX has
2n data inputs n select (or control) lines and 1 output.

It behaves like a channel selector.

Out A. S0 . S1 B. S0 .S1 C.S 0 . S1 D.S 0 .S1
A B C D

A 4-to-1 MUX: Out takes the value of A,B, C or D depending on the value of S (00, 01, 10, 11)

Out

S[1:0]

Out
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Adder
Half

Adder

2 inputs 2 outputs: sum and carry

ai 0 0 1 1

bi 0 1 0 1

ci+1 0 0 0 1

si 0 1 1 0

Half-adder truth table

Full

Adder

performs the addition in column i 3 inputs: ai, bi and ci 2 outputs: si and ci+1 ci is the carry in from bit position i-1 ci+1 is the carry out to bit position i+1
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a n 1 a n 2 ... a 1 a 0 b n 1 b n 2 ... b1 b 0 c n 1 c n 2 ... c1 0 s n 1 s n 2 ... s1 s 0

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Gate Level Full Adder

Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Ci 0 1 0 1 0 1 0 1 Ci+1 0 0 0 1 0 1 1 1 Si 0 1 1 0 1 0 0 1

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Full Adder - Expressions

si ai bi ci ci 1 ai .bi ci .(ai bi )
where

is exclusive OR . is the AND operation is the OR operation

- verify that this corresponds to the gate-level implementation.
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A 4-bit Ripple-Carry Adder

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Storage Elements: R-S Latch

0 1 1 0

The output a of the R-S latch can Conversely, the output a can be be set to 1 by momentarily setting set to 0 by keeping S at 1 and S to 0 while keeping R at 1. momentarily setting R to 0. When S is set back to 1 the output When R is set back to 1, the a stays at 1. output a stays at 0. The flip-flop (R-S latch) is a bi-stable element
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Storage Elements: Gated D Latch

The gated D latch is an extension of the R-S latch Two inputs: data (D) and write enable (WE) When the WE (write enable) is set to 1, the output of the latch is set to the value of D. The output is held until WE is asserted (set to 1) again.
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Registers

A 4-bit register made of four D latches

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Memory - 1
A large number of addressable fixed size locations

Address

Space

n bits allow the addressing of 2n memory locations.

Example: 24 bits can address 224 = 16,777,216 locations
(i.e. 16M locations). If each location holds 1 byte (= 8 bits) then the memory is 16MB. If each location holds one word (32 bits = 4 bytes) then it is 64 MB.

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Memory - 2
Addressability

Computers are either byte or word addressable - i.e. each memory location holds either 8 bits (1 byte), or a full standard word for that computer (16 bits for the LC-3, more typically 32 bits, though now many machines use 64 bit words). Normally, a whole word is written and read at a time:
If the computer is word addressable, this is simply a single address location. If the computer is byte addressable, and uses a multi-byte word, then the word address is conventionally either that of its most significant byte (big endian machines) or of its least significant byte (little endian machines).

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Building a Memory
A[1:0] D

Each Each

bit
location

is a gated D-latch consists of w bits (here w = 1) w = 8 if the memory is byte addressable

Addressing

WE

n locations means log2n address bits (here 2 bits => 4 locations) decoder circuit translates address into 1 of n locations

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Memory Example
A 22 by 3 bits memory:
two address lines: A[1:0] three data lines: D[2:0] one control line: WE

One gated D-latch

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Reading a location in memory

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Using Memory Building Blocks

Building an 8K byte memory using chips that are 2K by 4 bits.
CS = chip select:
A10-A0
2K x 4 bits 2K x 4 bits

CS
2K x 4 bits

CS
2K x 4 bits

A12-A11

d e c o d er

when set, it enables the addressing, reading and writing of that chip.

CS

CS

2K x 4 bits

2K x 4 bits

CS

CS

2K x 4 bits

2K x 4 bits

This is an 8KB byte addressable memory

CS

CS

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Memory One Word Wide

Use the previous memory block of 8K x 1 byte to build a memory that is 64K

words, with each location one word of 32 bits.

what are the address lines if the memory is word addressed? or byte addressed? A? - A?

8K x 1B

A? - A?

d e c o d er

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Sequential Logic Circuits - 1

The

concept of state

the state of a system is a snapshot of all relevant elements at a moment in time. a given system will often have only a finite number of possible states. e.g. the game of tic-tac-toe has only a certain number of possible dispositions of Xs and Os on the 3x3 grid. A given game of tic-tac-toe will progress through a subset of these possible states (until someone wins) - i.e. it traverses a specific path through state space, one move at a time. For many systems, we can define the rule which determine under what conditions a system can move from one state to another.

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Sequential Logic Circuits - 2

input
Combinational Logic Circuit

output

Storage Element

The output is a function of the current input and the previous state It is computed by the combinational logic circuit The state is stored in the storage element The new state is also a function of the previous state and the current input This can work only if we make transitions from one state to another at well-defined times - this is why they are called sequential circuits.
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Finite State Machines

Many

systems meet the following five conditions:

A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all allowed state transitions An explicit specification of the rules for each external output value
In

fact, as we will see, a microprocessor is a perfect candidate for description as a FSM.

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Finite State Machine Example - 1

0
all off 00

1
01

grp 1 on

DETOUR
0 0,1
all on 11

1
10

grp 1,2 on

Three groups of lights to be lit in a sequence: group 1 on, groups 1 & 2 on, all groups on, all off. The lights are on only if the main switch is on. Four states: so we need two bits to identify each state.

1
out1 out2 out3 2 d[1:0] Two bit Storage

switch
S
2

Combinational Logic Circuit

clock

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Finite State Machine Example - 2

When

is group 1 on?
out1 (d0.d1 d0.d1 d0.d1).S out2 (d0.d1 d0.d1).S out3 (d0.d1).S

in states 01, 10 and 11 - but only when the switch is on!

can you come up with a logic expression for d0 and d1?

When

do we switch to the next state?

the two bits of d[1:0] are updated at every clock cycle we have to make sure that the new state does not propagate to the combinational circuit input until the next clock cycle.
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Finite State Machine Example - 3

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The LC-3 as a Finite State Machine

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Data Path of the LC-3

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