Asynchronous Sequential Logic

1
 A sequential circuit is specified by a time sequence of
inputs, outputs, and internal states. In synchronous
sequential circuits, the change of internal state occurs in
response to the synchronized clock pulses. Asynchronous
sequential circuits do not use clock pulses. The change of
internal state occurs when there is a change in the input
variables. The memory elements in synchronous
sequential circuits are clocked flip-flops. The memory
elements in asynchronous sequential circuits are either
unclocked flip-flops or time-delay elements. The memory
capability of a time-delay device is due to the finite time it
takes for the signal to propagate through digital gates.
2
 An asynchronous sequential circuit quite often
resembles a combinational circuit with feedback. The
design of asynchronous sequential circuits is more
difficult than that of synchronous circuits because of the
timing problems involved in the feedback path. In a
properly designed synchronous system, timing problems
are eliminated by triggering all flip-flops with the pulse
edge. The change from one state to the next occurs
during the short time of the pulse transition. Since the
asynchronous circuit does not use a clock, the state of
the system is allowed to change immediately after the
input changes.
3
 Asynchronous sequential circuits are useful in a variety
of applications. They are used when speed of operation
is important, especially in those cases where the digital
system must respond quickly without having to wait
for a clock pulse. They are more economical to use in
small independent systems that require only a few
components, as it may not be practical to go to the
expense of providing a circuit for generating clock
pulses. Asynchronous circuits are useful in applications
where the input signals to the system may change at
any time, independently of an internal clock.

4
 The communication between two units, with each unit
having its own independent clock, must be done with
asynchronous circuits. the block diagram of an asynchronous
sequential circuit. It consists of a combinational circuit and
delay elements connected to form feedback loops. There are
n input variables, m output variables, and k internal states.
The delay elements can be visualized as providing short-term
memory for the sequential circuit. In a gate-type circuit, the
propagation delay that exists in the combinational circuit
path from input to output provides sufficient delay along the
feedback loop so that no specific delay elements are actually
inserted in the feedback path.

5
 The present-state and next-state variables in
asynchronous sequential circuits are customarily called
secondary variables and excitation variables,
respectively. The excitation variables should not be
confused with the excitable table used in the design of
clocked sequential circuits.

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7
 To ensure proper operation, asynchronous sequential
circuits must be allowed to attain a stable state before the
input is changed to a new value. Because of delays in the
wires and the gate circuits, it is impossible to have two or
more input variables change at exactly the same instant of
time without an uncertainty as to which one changes first.
Therefore, simultaneous changes of two or more variables
are usually prohibited. This restriction means that only
one input variable can change at anyone time and the time
between two input changes must be longer than the time it
takes the circuit to reach a stable state. This type of
operation is defined as fundamental mode.
8
 Fundamental-mode operation assumes that the input
signals change one at a time and only when the circuit
is in a stable condition. The analysis of asynchronous
sequential circuits consists of obtaining a table or a
diagram that describes the sequence of internal states
and outputs as a function of changes in the input
variables. A logic diagram manifests an asynchronous-
sequential-circuit behavior if it has one or more
feedback loops or if it includes unclocked flip-flops
(latches).

9
 Analysis Procedure
The analysis of asynchronous sequential circuits
consists of obtaining a table or a diagram that describes
the sequence of internal states and outputs as a function
of changes in the input variables. A logic diagram
manifests an asynchronous-sequential-circuit behavior if
it has one or more feedback loops or if it includes
unclocked flip-flops. An example of an asynchronous
sequential circuit with only gates is shown in figure on
the next slide. The circuit consists of one input variable,
x, and two internal states. The internal states have two
excitation variables, Y1 and Y2 and two secondary
variables, y1 and y2.
10
 Example:

11
 The delay associated with each feedback loop is
obtained from the propagation delay between each y
input and its corresponding Y output. Each logic gate
in the path introduces a propagation delay of about 2 to
10 nanoseconds. The wires that conduct electrical
signals introduce approximately one-nanosecond delay
for each foot of wire. Thus, no additional external
delay elements are necessary when the combinational
circuit and the wires in the feedback path provide
sufficient delay.

12
 The analysis of the circuit starts by considering the
excitation variables as outputs and the secondary
variables as inputs. Derive the Boolean expressions for
the excitation variables as a function of the input and
secondary variables. The analysis of the circuit starts
by considering the excitation variables as outputs and
the secondary variables as inputs. Then derive the
Boolean expressions for the excitation variables as a
function of the input and secondary variables. These
can be readily obtained from the logic diagram.

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 Y1 = x y1 + x' y2 & Y2 = x y1’ + x‘ y2
The next step is to plot the Y1 and Y2 functions in a
map,

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 In general, if a change in the input takes the circuit to an
unstable state, the value of y will change (while x remains
the same) until it reaches a stable (circled) state. Note the
difference between a synchronous and an asynchronous
sequential circuit. Using this type of analysis for the
remaining squares of the transition table, we find that the
circuit repeats the sequence of states 00, 01, 11, 10 when the
input repeatedly alternates between 0 and 1. Note the
difference between a synchronous and an asynchronous
sequential circuit. In a synchronous system, the present state
is totally specified by the flip-flop values and does not
change if the input changes while the clock pulse is inactive.

15
 In an asynchronous circuit, the internal state can change
immediately after a change in the input. Because of this, it
is sometimes convenient to combine the internal state with
the input value together and call it the total state of the
circuit. The circuit whose transition table is shown in
Figure (c) has four stable total states, y1 y2 x = 000, 011,
110, and 101, and four unstable total states, 001, 010, 111,
and 100. The transition table of asynchronous sequential
circuits is similar to the state table used for synchronous
circuits. If we regard the secondary variables as the
present state and the excitation variables as the next state,
we obtain the state table, as shown in Table 1.
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 Table 1
Present state Next state
y1 y2 x=0 x=1
0 0 0 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 1 1 1 1 0

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 This table provides the same information as the
transition table. There is one restriction that applies to
the asynchronous case but does not apply to the
synchronous case. In the asynchronous transition table,
there usually is at least one next state entry that is the
same as the present-state value in each row. Otherwise,
all the total states in that row will be unstable.

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 Transition Table
Q = X X ’ + X ’ X Q + X Q Q ’
1+ 1 2 1 2 2 2 1 2

Q = X ’ X Q ’ + X Q + X Q
2+ 1 2 1 1 2 2 2

Z = X  Q  Q
1 1 2

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 Transition Table and Flow table

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 Output table

22
 Transition Table
The procedure for obtaining a transition table from the
circuit diagram of an asynchronous sequential circuit is as
follows:
1. Determine all feedback loops in the circuit.
2. Designate the output of each feedback loop with variable
Y1 and its corresponding input with yi for i = 1,2, ... , k,
where k is the number of feedback loops in the circuit.
3. Derive the Boolean functions of all Y's as a function of
the external inputs and the y's.
4. Plot each Y function in a map, using the y variables for
the rows and the external inputs for the columns.

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 5. Combine all the maps into one table showing the
value of Y = Y1 Y2    Yk inside each square.
6. Circle those values of Y in each square that are
equal to the value of y = y1 y2    yk in the same
row.
Once the transition table is available, the behavior of
the circuit can be analyzed by observing the state
transition as a function of changes in the input
variables.

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 Flow table
During the design of asynchronous sequential circuits, it is
more convenient to name the states by letter symbols
without making specific reference to their binary values.
Such a table is called a flow table. A flow table is similar
to a transition table except that the internal states are
symbolized with letters rather than binary numbers. The
flow table also includes the output values of the circuit for
each stable state. The table of Fig. (a) is called a primitive
flow table because it has only one stable state in each row.
Figure (b) shows a flow table with more than one stable
state in the same row. It has two states, a and b; two
inputs, x1 and x2; and one output, z.
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26
 The binary value of the output variable is indicated
inside the square next to the state symbol and is
separated by a comma. From the flow table, the
behavior of the circuit is seen. If x1 = 0, the circuit is in
state a. If x1 goes to 1 while x2 is 0, the circuit goes to
state b. With inputs x1 x2, = 11, the circuit may be
either in state a or state b. If in state a, the output is 0,
and if in state b, the output is 1. State b is maintained if
the inputs change from 10 to 11. The circuit stays in
state a if the inputs change from 01 to 11. In order to
obtain the circuit described by a flow table, it is
necessary to assign to each state a distinct binary value.
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 This assignment converts the flow table into a
transition table from which we can derive the logic
diagram. Assign binary 0 to state a and binary 1 to
state b. The result is the transition table of Fig. (a).

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 The output map shown in Fig. (b) is obtained directly
from the output values in the flow table. The excitation
function Y and the output function z are simplified by
means of the two maps.

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 Logic diagram for the flow table

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 This example demonstrates the procedure for obtaining
the logic diagram from a given flow table. There are
several difficulties associated with the binary state
assignment and with the output assigned to the
unstable states.

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 Race Condition
A race condition is said to exist in an asynchronous
sequential circuit when two or more binary state
variables change value in response to a change in an
input variable. When unequal delays are encountered,
a race condition may cause the state variables to
change in an unpredictable manner. For example, if the
state variables must change from 00 to 11, the
difference in delays may cause the first variable to
change faster than the second, with the result that the
state variables change in sequence from 00 to 10 and
then to 11. If the second variable changes faster than
the first, the state variables will change from 00 to 01
32 and then to 11.
 Thus, the order by which the state variables change
may not be known in advance. If the final stable state
that the circuit reaches does not depend on the order in
which the state variables change, the race is called a
noncritical race. If it is possible to end up in two or
more different stable states, depending on the order in
which the state variables change, then it is a critical
race. For proper operation, critical races must be
avoided.

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 Non-critical races

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 Critical races

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 Races may be avoided by making a proper binary
assignment to the state variables. The state variables
must be assigned binary numbers in such a way that
only one state variable can change at anyone time
when a state transition occurs in the flow table. Races
can be avoided by directing the circuit through
intermediate unstable states with a unique state-
variable change. When a circuit goes through a unique
sequence of unstable states, it is said to have a cycle.
The transition table of part (a) gives a unique sequence
that terminates in a total stable state 101.

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 Unique state sequence

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 The table in (b) shows that even though the state
variables change from 00 to 11, the cycle provides a
unique transition from 00 to 01 and then to 11.

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 Care must be taken when using a cycle that it
terminates with a stable state. If a cycle does not
terminate with a stable state, the circuit will keep
going from one unstable state to another, making the
entire circuit unstable. This is demonstrated in Fig. (c).

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 Unstable cycle race

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 Because of the feedback connection that exists in
asynchronous sequential circuits, care must be taken to
ensure that the circuit does not become unstable. An
unstable condition will cause the circuit to oscillate
between unstable states. The transition-table method of
analysis can be useful in detecting the occurrence of
instability.

41
 Circuits with latches
Historically, asynchronous sequential circuits were known
and used before synchronous circuits were developed. The
first practical digital systems were constructed with relays,
which are more adaptable to asynchronous-type operations.
For this reason, the traditional method of asynchronous-
circuit configuration has been with components that are
connected to form one or more feedback loops. As
electronic digital circuits were developed, it was realized
that the flip-flop circuit could be used as a memory
element in sequential circuits. Asynchronous sequential
circuits can be implemented by employing a basic flip-flop
commonly referred to as an SR latch.

42
 The use of SR latches in asynchronous circuits
produces a more orderly pattern, which may result in a
reduction of the circuit complexity. An added
advantage is that the circuit resembles the synchronous
circuit in having distinct memory elements that store
and specify the internal states.

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 SR Latch
The SR latch is a digital circuit with two inputs, S and
R and two cross-coupled NOR gates or two cross-
coupled NAND gates. The Boolean function for the
output is
Y = [(S + y)' + R]' = (S + y)R' = SR' + R'y

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 Plotting Y, the transition table for the circuit for NOR
gates.

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 With SR = 10, the output Q = Y = 1 and the latch is said
to be set. Changing S to 0 leaves the circuit in the set
state. With SR = 01, the output Q = Y = 0 and the latch
is said to be reset. A change of R back to 0 leaves the
circuit in the reset state. These conditions are also listed
in the truth table. The circuit exhibits some difficulty
when both S and R are equal to 1. From the truth table,
we see that both Q and Q' are equal to 0, a condition that
violates the requirement that these two outputs be the
complement of each other. Moreover, from the transition
table, we note that going from SR = 11 to SR = 00
produces an unpredictable result.
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 If S goes to 0 first, the output remains at 0, but if R
goes to 0 first, the output goes to 1. In normal
operation, we must make sure that 1's are not applied
to both the Sand R inputs simultaneously. This
condition can be expressed by the Boolean function
SR = 0, which states that the ANDing of S and R must
always result in a 0. note that when we OR the
Boolean expression SR' with SR, the result is the
single variable S.
SR' + SR = S(R' + R) = S

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 From this we deduce that SR' = S when SR = 0.
Therefore, the excitation function derived previously,
Y = SR' + R'y
can be expressed as,
Y = S + R'y when SR = 0
To analyze a circuit with an SR latch, check that the
Boolean condition SR = 0 holds at all times. Then use
the reduced excitation function to analyze the circuit.
However, if it is found that both S and R can be equal
to 1 at the same time, then it is necessary to use the
original excitation function.
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 Transition table for SR latch using NAND gates

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 SR latch with NAND gates

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 The NAND latch operates with both inputs normally at
1 unless the state of the latch has to be changed. The
application of 0 to R causes the output Q to go to 0,
thus putting the latch in the reset state. After the R
input returns to 1, a change of S to 0 causes a change
to the set state. The condition to be avoided here is that
both Sand R not be 0 simultaneously. This condition is
satisfied when S'R' = 0. The excitation function for the
circuit is
y = [S(Ry)']' = S' + Ry

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 Analysis example

52
 The circuit shown has two SR latches with outputs Y1
and Y2. There are two inputs, x1 and x2 and two
external feedback loops giving rise to the secondary
variables y1 and y2. Note that this circuit resembles a
conventional sequential circuit with latches behaving
like flip-flops without clock pulses. The analysis of the
circuit requires that we first obtain the Boolean
functions for the Sand R inputs in each latch.
S1 = x1 y2 R1 = x1’ x2’
S2 = x1 x2 R2 = x2’ y1

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 Check whether the condition SR = 0 is satisfied to
ensure proper operation.
S1 R1 = x1 y2 x1’ x2’ = 0
S2 R2 = x1 x2 x2’ y1 = 0
The result is 0 because x1 x1’ = x2 x2’ = 0. The next
step is to derive the transition table of the circuit.
Remember that the transition table specifies the value
of Y as a function of y and x. The excitation functions
are derived from the relation Y = S + R' y.

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 Y1 = S1 + R1’y1 = x1y2 + (x1 + x2)y1 = x1y2 + x1y1 +
x2y1
Y2 = S2 + R2’y2 = x1x2 + (x2 + y1’)y2 = x1x2 + x2y2 +
y1’y2
In developing a composite map for Y = Y1Y2, the
variables are assigned to the rows in the map, and the x
variables are assigned to the columns, as shown.

55
56
 The Boolean functions of Y1 and Y2 are used to plot
the composite map for Y. There is a critical race
condition when the circuit is initially in total state
y1y2x1x2 = 1101 and x2 changes from 1 to 0. If Y1
changes to 0 before Y2 the circuit goes to total state
0100 instead of 0000. However, with approximately
equal delays in the gates and latches, this undesirable
situation is not likely to occur.

57
 ASL using S-R latch
The procedure for analyzing an asynchronous
sequential circuit with SR latches can be summarized
as follows:
1. Label each latch output with Yi and its external
feedback path (if any) with yi for i = 1,2, ..., k.
2. Derive the Boolean functions for the Si and Ri inputs
in each latch.
3. Check whether SR = 0 for each NOR latch or
whether S'R' = 0 for each NAND latch. If this
condition is not satisfied, there is a possibility that
the circuit may not operate properly.
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 4. Evaluate Y = S + R'y for each NOR latch or Y = S'
+ Ry for each NAND latch.
5. Construct a map with the y's representing the rows
and the x inputs representing the columns.
6. Plot the value of Y = Y1 Y2 • • • Yk, in the map.
7. Circle all stable states where Y = y. The resulting
map is then the transition table.

59
 The implementation of a sequential circuit with SR
latches is a procedure for obtaining the logic diagram
from a given transition table. The procedure requires
that we determine the Boolean functions for the Sand
R inputs of each latch. The logic diagram is then
obtained by drawing the SR latches and the logic gates
that implement the Sand R functions. The general
procedure for implementing a circuit with SR latches
from a given transition table can now be summarized
as follows:

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 Summarized Procedures
1. Given a transition table that specifies the excitation
function Y = Y1 Y2    Yk derive a pair of maps for
Si and Ri for each i = 1,2, ... ,k. (latch excitation table)
2. Derive the simplified Boolean functions for each Si
and Ri. Care must be taken not to make Si and Ri
equal to 1 in the same minterm square.
3. Draw the logic diagram using k latches together with
the gates required to generate the S and R Boolean
functions. For NOR latches, use the S and R Boolean
functions obtained in step 2. For NAND latches, use
the complemented values of those obtained in step 2.

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 Design Procedures
The design of an asynchronous sequential circuit starts
from the statement of the problem and culminates in a
logic diagram. There are a number of design steps that
must be carried out in order to minimize the circuit
complexity and to produce a stable circuit without critical
races. Briefly, the design steps are as follows. A primitive
flow table is obtained from the design specifications. The
flow table is reduced to a minimum number of states. The
states are then given a binary assignment from which the
transition table is obtained. Finally, from the transition
table, derive the logic diagram as a combinational circuit
with feedback or as a circuit with SR latches.
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From the previous example
From the previous example
Design with SR Latch using NOR
Design with SR Latch using NOR
 Design Example
It is necessary to design a gated latch circuit with two
inputs, G (gate) and D (data), and one output, Q.
Binary information present at the D input is transferred
to the Q output when G is equal to 1. The Q output
will follow the D input as long as G = 1. When G goes
to 0, the information that was present at the D input at
the time the transition occurred is retained at the Q
output. The gated latch is a memory element that
accepts the value of D when G = 1 and retains this
value after G goes to 0. Once G = 0, a change in D
does not change the value of the output Q.

67
 As defined, a primitive flow table is a flow table with
only one stable total state in each row. Remember that
a total state consists of the internal state combined with
the input. The derivation of the primitive flow table
can be facilitated if a table with all possible total states
is first formed in the system. This is shown in the table
for the gated latch. Each row in the table specifies a
total state, which consists of a letter designation for the
internal state and a possible input combination for D
and G. The output Q is also shown for each total state.

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 Gated Latch total state table

69
 Note that simultaneous transitions of two input
variables, such as from 01 to 10 or from 11 to 00, are
not allowed in fundamental-mode operation. The
primitive flow table for the gated latch has one row for
each state and one column for each input combination.
Fill in one square in each row belonging to the stable
state in that row. These entries are determined from the
gated Latch total state table. This information is entered
in the flow table in the first row and second column.
Similarly, the other five stable states together with their
output are entered in the corresponding input columns.

70
 Next, note that since both inputs are not allowed to
change simultaneously, enter dash marks in each row
that differs in two or more variables from the input
variables associated with the stable state. This will
eventually result in a don't-care condition for the next
state and output in this square. Following this
procedure, we fill in a second square in each row of
the primitive flow table. Next it is necessary to find
values for two more squares in each row. The
comments listed in the table may help in deriving the
necessary information.

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 Therefore, an unstable state c is shown in column 00 and
rows a and d in the flow table. The output is marked with a
dash to indicate a don't-care condition. The interpretation
of this is that if the circuit is in stable state a and the input
changes from 01 to 00, the circuit first goes to an unstable
next state c, which changes the present state value from a to
c, causing a transition to the third row and first column of
the flow table. The unstable state values for the other
squares are determined in a similar manner. All outputs
associated with unstable states are marked with a dash to
indicate don't-care conditions. The assignment of actual
values to the outputs is discussed further after the design
example is completed.
72
73
 The primitive flow table has only one stable state in each
row. The table can be reduced to a smaller number of rows if
two or more stable states are placed in the same row of the
flow table. The grouping of stable states from separate rows
into one common row is called merging. Merging a number
of stable states in the same row means that the binary state
variable that is ultimately assigned to the merged row will
not change when the input variable changes. This is because
in a primitive flow table, the state variable changes every
time the input changes, but in a reduced flow table, a change
of input will not cause a change in the state variable if the
next stable state is in the same row.

74
 In order to complete the design example without going
through the formal procedure, we will apply the
merging process by using a simplified version of the
merging rules. Two or more rows in the primitive flow
table can be merged into one row if there are non-
conflicting states and outputs in each of the columns.
Whenever one state symbol and don't-care entries are
encountered in the same column, the state is listed in
the merged row. Moreover, if the state is circled in one
of the rows, it is also circled in the merged row. The
output value is included with each stable state in the
merged row.
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 Simplified merging rules
The letter symbols for the states can be retained to
show the relationship between the reduced and
primitive flow tables. The other alternative is to define
a common letter symbol for all the stable states of the
merged rows. Thus, states c and dare replaced by state
a, and states e and f are replaced by state b.

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 Both alternatives are shown here.

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 Reduced flow table

78
 In order to obtain the circuit described by the reduced
flow table, it is necessary to assign to each state a
distinct binary value. This assignment converts the
flow table into a transition table. In the general case, a
binary state assignment must be made to ensure that
the circuit will be free of critical races. Assigning 0 to
state a and 1 to state b in the reduced flow table, results
in the transition table and output map for the gated d
latch.

79
 Transition table and output map for the gated latch.

80
 The transition table is, in effect, a map for the
excitation variable Y. The simplified Boolean function
for Y is then obtained from the map.
Y = DG + G'y
There are two don't-care outputs in the final reduced
flow table. If we assign values to the output, it is
possible to make output Q equal to the excitation
function Y. If we assign the other possible values to the
don't-care outputs, we can make output Q equal to y.

81
 Gated latch logic diagram

82
 Input maps using SR latch

83
 Logic circuit implementation using SR latch

84
 Assigning unstable states
The stable states in a flow table have specific output
values associated with them. The unstable states have
unspecified output entries designated by a dash. The
output values for the unstable states must be chosen so
that no momentary false outputs occur when the circuit
switches between stable states. This means that if an
output variable is not supposed to change as the result of
a transition, then an unstable state that is a transient state
between two stable states must have the same output
value as the stable states. If an output variable is to
change value as a result of a state change, then this
variable is assigned a don't-care condition.
85
 Output assignments for unstable states

86
 The procedure for making the assignment to outputs
associated with unstable states can be summarized as
follows:
1. Assign a 0 to an output variable associated with an
unstable state that is a transient state between two
stable states that have a 0 in the corresponding output
variable.
2. Assign a I to an output variable associated with an
unstable state that is a transient state between two
stable states that have a I in the corresponding output
variable.
87
 3. Assign a don't-care condition to an output variable
associated with an unstable state that is a transient
state between two stable states that have different
values (0 and 1 or I and 0) in the corresponding
output variable.

88
 Summary of Design Procedure
The design of asynchronous sequential circuits can be
carried out by using the procedure illustrated in the
previous example. Some of the design steps need
further elaboration and are explained in the following
sections. The procedural steps are as follows.
1. Obtain a primitive flow table from the given design
specifications. This is the most difficult part of the
design because it is necessary to use intuition and
experience to arrive at the correct interpretation of
the problem specifications.

89
 2. Reduce the flow table by merging rows in the
primitive flow table. A formal procedure for merging
rows in the flow table is given.
3. Assign binary state variables to each row of the
reduced flow table to obtain the transition table. The
procedure of state assignment that eliminates any
possible critical races is given.
4. Assign output values to the dashes associated with
the unstable states to obtain the output maps.

90
 5. Simplify the Boolean functions of the excitation and
output variables and draw the logic diagram. The
logic diagram can be drawn using SR latches, as
shown.

91
 Reduction of State and Flow Tables
The procedure for reducing the number of internal states
in an asynchronous sequential circuit resembles the
procedure that is used for synchronous circuits. The
state-reduction procedure for completely specified state
tables is based on the algorithm that two states in a state
table can be combined into one if they can be shown to
be equivalent. Two states are equivalent if for each
possible input, they give exactly the same output and go
to the same next states or to equivalent next states.
There are occasions when a pair of states do not have
the same next states, but, nonetheless, go to equivalent
next states.
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 Merging of the Flow Table
There are occasions when the state table for a sequential
circuit is incompletely specified. This happens when
certain combinations of inputs or input sequences may
never occur because of external or internal constraints.
In such a case, the next states and outputs that should
have occurred if all inputs were possible are never
attained and are regarded as don't-care conditions.
Although synchronous sequential circuits may
sometimes be represented by incompletely specified
state tables, our interest here is with asynchronous
sequential circuits where the primitive flow table is
always incompletely specified.
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 Incompletely specified states can be combined to reduce
the number of states in the flow table. Such states cannot
be called equivalent, because the formal definition of
equivalence requires that all outputs and next states be
specified for all inputs. Instead, two incompletely
specified states that can be combined are said to be
compatible. Two states are compatible if for each possible
input they have the same output whenever specified and
their next states are compatible whenever they are
specified. All don't-care conditions marked with dashes
have no effect when searching for compatible states as
they represent unspecified conditions.
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 The process that must be applied in order to find a suitable
group of compatibles for the purpose of merging a flow
table can be divided into three procedural steps.
1. Determine all compatible pairs by using the implication
table.
2. Find the maximal compatibles using a merger diagram.
3. Find a minimal collection of compatibles that covers all
the states and is closed.
The minimal collection of compatibles is then used to
merge the rows of the flow table.

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