Chapter 5 Low Noise Amplifiers

5.1 General Considerations 5.2 Problem of Input Matching 5.3 LNA Topologies 5.4 Gain Switching 5.5 Band Switching 5.6 High IP2 LNAs 5.7 Nonlinearity Calculations

Behzad Razavi, RF Microelectronics.

Prepared by Bo Wen, UCLA

Chapter Outline

Basic LNA Topologies

CS Stage with Inductive Load CS Stage with Resistive Feedback CG Stage CS Stage with Inductive Degeneration

Alternative LNA Topologies

Variants of CS LNA Noise-Cancelling LNAs Differential LNAs

Nonlinearity of LNAs
Nonlinearity Calculations Differential and QuasiDifferential LNAs

Chapter 5 Low Noise Amplifiers

General Considerations: Noise Figure

The noise figure of the LNA directly adds to that of the receiver.
It is expected that the LNA contributes 2 to 3 dB of noise figure. Consider the simple example shown below:

A noise figure of 2 dB with respect to a source impedance of 50 translates to: an extremely low value.
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Example of Metal Resistance and Noise Figure

A student lays out an LNA and connects its input to a pad through a metal line 200 m long. In order to minimize the input capacitance, the student chooses a width of 0.5 m for the line. Assuming a noise figure of 2 dB for the LNA and a sheet resistance of 40 m/ for the metal line, determine the overall noise figure. Neglect the input-referred noise current of the LNA.
We draw the equivalent circuit as shown in figure below, pretending that the line resistance, RL, is part of the LNA. The total input-referred noise voltage of the circuit inside the box is therefore equal to V n,in2+4kTRL. We thus write

where NFLNA denotes the noise figure of the LNA without the line resistance. Since NFLNA = 2 dB 1.58 and RL = (200/0.5) 40 m/ = 16 , we have

Chapter 5 Low Noise Amplifiers

General Considerations: Gain

The gain of the LNA must be large enough to minimize the noise contribution of subsequent stages, specifically, the downconversion mixer(s).
The noise and IP3 of the stage following the LNA are divided by different LNA gains. Assuming a unity voltage gain for the mixer for simplicity, The overall noise figure is thus equal to

In figure above (right),

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General Considerations: Input Return Loss

The quality of the input match is expressed by the input return loss, defined as the reflected power divided by the incident power. For a source impedance of RS, the return loss is given by:

Figure above plots contours of constant in the Zin plane. Each contour is a circle with its center shown.
Chapter 5 Low Noise Amplifiers

General Considerations: Stability

A parameter often used to characterize the stability of circuits is the Stern stability factor, defined as:

A cascade stage exhibits a high reverse isolation, i.e., S12 0. If the output impedance is relatively high so that S22 1, determine the stability conditions.
With S12 0 and S22 1,

and hence

In other words, the forward gain must not exceed a certain value. For < 1, we have concluding that the input resistance must remain positive.
Chapter 5 Low Noise Amplifiers

General Considerations: Linearity

In most applications, the LNA does not limit the linearity of the receiver.
An exception to the above rule arises in full-duplex systems:

Leakages through the filter and the package yield a finite isolation between ports 2 and 3 as characterized by an S32 of about -50 dB. The received signal may be overwhelmed.

Chapter 5 Low Noise Amplifiers

General Considerations: Bandwidth

The LNA must provide a relatively flat response for the frequency range of interest, preferably with less than 1 dB of gain variation. The LNA -3-dB bandwidth must therefore be substantially larger than the actual band so that the roll-off at the edges remains below 1 dB.

An 802.11a LNA must achieve a -3-dB bandwidth from 5 GHz to 6 GHz. If the LNA incorporates a second-order LC tank as its load, what is the maximum allowable tank Q?
As illustrated in figure below, the fractional bandwidth of an LC tank is equal to /0 = 1/Q. Thus, the Q of the tank must remain less than 5.5 GHz/1 GHz = 5.5.

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Band Switching
LNA designs that must achieve a relatively large fractional bandwidth may employ a mechanism to switch the center frequency of operation.
As depicted below, an additional capacitor, C2, can be switched into the tank, thereby changing the center frequency

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Problem of Input Matching: Input Admittance of a CS Stage

LNAs are typically designed to provide a 50-W input resistance and negligible input reactance. This requirement limits the choice of LNA topologies.
The real and imaginary parts of the input admittance are, respectively, equal to:

Why did we compute the input admittance rather than the input impedance for the circuit of figure above.
The choice of one over that other is somewhat arbitrary. In some circuits, it is simpler to compute Yin. Also, if the input capacitance is cancelled by a parallel inductor, then Im{Yin} is more relevant. Similarly, a series inductor would cancel Im{Zin}. We return to these concepts later in this chapter.
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Resistive Termination for Matching

Such a topology is designed in three steps: (1) M1 and RD provide the required noise figure and gain (2) RP is placed in parallel with the input to provide Re{Zin} = 50 (3) an inductor is interposed between RS and the input to cancel Im{Zin}.
express the total output noise as:

the noise figure is given by:

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Example of Input Matching by Transforming a Large Resistance Down ()

A student decides to defy the above observation by choosing a large RP and transforming its value down to RS. The resulting circuit is shown below (left), where C1 represents the input capacitance of M1. (The input resistance of M1 is neglected.) Can this topology achieve a noise figure less than 3 dB?
Consider the more general circuit in figure below (right), where H(s) represents a lossless network similar to L1 and C1. Since it is desired that Zin = RS, the power delivered by Vin to the input port of H(s) is equal to (Vin,rms/2)2/RS. This power must also be delivered to RP :

It follows that

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Example of Input Matching by Transforming a Large Resistance Down ()

Let us now compute the output noise with the aid of figure below (left). The output noise due to the noise of RS is readily obtained

How about the noise of RP? We must first determine the value of Rout. We draw the circuit as depicted above (middle) and recall that a passive reciprocal network exhibiting a real port impedance of RS also produces a thermal noise of 4kTRS. From the equivalent circuit shown above (right), we note that the noise power delivered to the RS on the left is equal to kT.

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LNA Topologies: Overview

Our preliminary studies thus far suggest that the noise figure, input matching, and gain constitute the principal targets in LNA design. We present a number of LNA topologies and analyze their behavior with respect to these targets.

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Common-Source Stage with Inductive Load

In general, the trade-off between the voltage gain and the supply voltage in the CS stage with resistive load makes it less attractive as the latter scales down with technology. For example, at low frequencies,

To circumvent the trade-off expressed above and also operate at higher frequencies, the CS stage can incorporate an inductive load.

Can operate with very low supply voltages L1 resonates with the total capacitance at the output node, affording a much higher operation frequency than does the resistively-loaded counterpart
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Input Matching of CS Stage with Inductive Load ()

We redraw the circuit as depicted above (right) the inductor loss is modeled by a series resistance, RS, The tank impedance is given by

Adding the voltage drop across CF to the tank voltage, we have

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Input Matching of CS Stage with Inductive Load ()

Substitution of ZT gives:

For s = j:

Since the real part of a complex fraction (a+jb)/(c+jd) is equal to (ac+bd)/(c2 +d2), we have

It is thus possible to select the values so as to obtain Re{Zin} = 50

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Neutralization of CF by LF
The feedback capacitance gives rise to a negative input resistance at other frequencies, potentially causing instability.

The numerator falls to zero at a frequency given by

Thus, at this frequency (if it exists), Re{Zin} changes sign.

It is possible to neutralize the effect of CF in some frequency range through the use of parallel resonance. Will introduce significant parasitic capacitances at the input and output and degrading the performance.
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Common-Source Stage with Resistive Feedback

If channel-length modulation is neglected, we have: We must choose: In figure above (right):

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Noise Figure of CS Stage with Resistive Feedback

The noise of RF appears at the output:

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Example of CS Stage with Active Load

In the circuit of figure below, the PMOS current source is converted to an active load, amplifying the input signal. The idea is that, if M2 amplifies the input in addition to injecting noise to the output, then the noise figure may be lower. Neglecting channel-length modulation, calculate the noise figure. (Current source I1 defines the bias current and C1 establishes an ac ground at the source of M2).
For small-signal operation, M1 and M2 appear in parallel, behaving as a single transistor with a transconductance of gm1 + gm2. Thus, for input matching, gm1 + gm2 = 1/RS. The noise figure is still given by previous equation, except that (gm1 + gm2)RS = . That is,

This circuit is therefore superior, but it requires a supply voltage equal to VGS1 + |VGS2| + VI1, where VI1 denotes the voltage headroom necessary for I1.

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Common-Gate Stage
The low input impedance of the common-gate (CG) stage makes it attractive for LNA design.

The voltage gain from X to the output node at the output resonance frequency is then equal to: And noise:

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Example of Noise in CG Stage with Different Biasing ( )

We wish to provide the bias current of the CG stage by a current source or a resistor. Compare the additional noise in these two cases.
For a given Vb1 and VGS1, the source voltages of M1 in the two cases are equal and hence VDS2 is equal to the voltage drop across RB (=VRB). Operating in saturation, M2 requires that VDS2 VGS2 - VTH2. We express the noise current of M2 as

And that of RB as

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Example of Noise in CG Stage with Different Biasing ( )

We wish to provide the bias current of the CG stage by a current source or a resistor. Compare the additional noise in these two cases.
Since VGS2-VTH2 VRB, the noise contribution of M2 is about twice that of RB (for 1). Additionally, M2 may introduce significant capacitance at the input node. The use of a resistor is therefore preferable, so long as RB is much greater than RS so that it does not attenuate the input signal. Note that the input capacitance due to M1 may still be significant. We will return to this issue later. Figure 5.18 shows an example of proper biasing in this case.

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Input Impedance of CG Stage in the Presence of rO

The positive feedback through rO raises the input impedance

Thus, the term R1/(gmrO) may become comparable with or even exceed the term 1/gm, yielding an input resistance substantially higher than 50

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Example of Input Impedance of CG Stage

Neglecting the capacitances of M1 in figure above, plot the input impedance as a function of frequency.

Solution:
At very low or very high frequencies, the tank assumes a low impedance, yielding Rin = 1/gm [or 1/(gm + gmb) if body effect is considered]. Figure below depicts the behavior.

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More about Channel-Length Modulation

With the strong effect of R1 on Rin, we must equate the actual input resistance to RS to guarantee input matching:

The voltage gain of the CG stage with a finite rO is expressed as

If rO and R1 are comparable, then the voltage gain is on the order of gmrO=4, a very low value.

In summary, the input impedance of the CG stage is too low if channel-length modulation is neglected and too high if it is not. In order to alleviate the above issue, the channel length of the transistor can be increased
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Cascode CG Stage
An alternative approach to lowering the input impedance is to incorporate a cascode device

If gmrO >>1, then

R1 is divided by the product of two intrinsic gains, its effect remains negligible. Similarly, the third term is much less than the first if gm1 and gm2 are roughly equal. Thus, Rin 1/gm1.
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Issues of Cascode CG Stage: Voltage Headroom Limitation

The two transistors M1 and M2 consume a voltage headroom of one VGS plus one overdrive (VGS1 -VTH1). In order to avoid the noise-headroom trade-off imposed by RB, and also cancel the input capacitance of the circuit, CG stages often employ an inductor for the bias path.

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Cascode CS Stage with Inductive Degeneration

Add a cascode transistor in the output branch to suppress the effect of negative resistance. The voltage gain:

The impedance seen at the source of M2, RX rises sharply at the output resonance frequency.

The voltage gain from the gate to the drain of M1:

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Design Procedure ()
The procedure begins with four knowns: the frequency of operation, 0, the value of the degeneration inductance, L1, the input pad capacitance, Cpad, and the value of the input series inductance, LG.
Governing the design are the following equations:

In the next step, the dimensions of the cascode device are chosen equal to those of the input transistor. The design procedure continues with selecting a value for LD such that it resonates at 0 with the drain-bulk and drain-gate capacitances of M2, the input capacitance of the next stage, and the inductorss own parasitic capacitance.

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Design Procedure ()
In the last step of the design, we must examine the input match. Due to the Miller multiplication of CGD1 , it is possible that the real and imaginary parts depart from their ideal values, necessitating some adjustment in LG.
Alternatively, the design procedure can begin with known values for NF and L1 and the following two equations:

The overall LNA appears as shown on right:

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Variants of Common-Gate LNA: CG LNA with Feedback ()

The block having a gain (or attenuation factor) of senses the output voltage and subtracts a fraction thereof from the input.
If channel length modulation and body effect are neglected, the closed-loop input impedance is equal to:

At resonance,

To calculate noise figure, we first calculate the gain with the aid of the circuit on the left.

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Variants of Common-Gate LNA: CG LNA with Feedback ()

For output noise calculation, we construct the circuit of figure on the right

The NF can be lowered by raising gm

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CG LNA with Feedforward

The block having a gain (or attenuation factor) of senses the output voltage and subtracts a fraction thereof from the input.

with the noise of the gain stage A:

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CG Stage with Transformer Feedforward

For a coupling factor of k between the primary and the secondary and a turns ratio of n, the transformer provides a voltage gain of kn.

On-chip transformer geometries make it difficult to achieve a voltage gain higher than roughly 3, even with stacked spirals
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Noise-Canceling LNAs: Basic Ideas

Noise-canceling LNAs aim to cancel the term representing the contribution of the input transistor in the noise figure of LNAs.

First identify two nodes at which the signal appears with opposite polarities but the noise of the input transistor appears with the same polarity. Then their voltages can be properly scaled and summed such that the signal components add and the noise components cancel.
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Chapter 5 Low Noise Amplifiers

Noise-Canceling LNAs: Noise Figure

The NF can be lowered by raising gm

We obtain the noise figure as:

Since A1 = 1 + RF/RS

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Noise-Canceling LNAs: Frequency-Dependent NF and Circuit Implementation

It can be proved that the frequency-dependent noise figure is expressed as

where NF(0) is given by equation in previous NF calculation and f0 = 1/(RSCin)

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Example of an Alternative Implementation

Figure below shows an alternative implementation of a noise-canceling LNA that also performs single ended to differential conversion. Neglecting channel-length modulation, determine the condition for noise cancellation and derive the noise figure.
The circuit follows the noise cancellation principle because (a) the noise of M1, Vn1, sees a source follower path to node X and a common-source path to node Y , exhibiting opposite polarities at these two nodes, and (b) the signal sees a common-gate path through X and Y , exhibiting the same polarity. For noise cancellation, we must have

and, since gm1 = 1/RS

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Balun Issues
External baluns with a low loss (e.g., 0.5 dB) in the gigahertz range are available from manufacturers, but they consume board space and raise the cost. Integrated baluns, on the other hand, suffer from a relatively high loss and large capacitances.

The resistance and capacitance associated with the spirals and the sub-unity coupling factor make such baluns less attractive.
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Use of 1-to-N Balun in an LNA

A student attempts to use a 1-to-N balun with a differential CS stage so as to amplify the input voltage by a factor of N and potentially achieve a lower noise figure. Compute the noise figure in this case.
Since still half of the noise current of each input transistor flows to the output node, the noise power measured at each output is given by

The gain from Vin to the differential output is now equal to NR1/(2L10). Doubling the above power, dividing by the square of the gain, and normalizing to 4kTRS, we have

We note, with great distress, that the first two terms have risen by a factor of N2

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Realization of Baluns with Non-Unity Turns Ratio

On-chip baluns with a non-unity turns ratio are difficult to design and suffer from a higher loss and a lower coupling factor.

Stacked Spirals

Embedded Spirals

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