Scribd
Upload
43 views12 pages

Cs370 - Spring 2003 Programmable Logic Devices Pals/Plas

The document discusses Programmable Array Logic (PAL) and Programmable Logic Array (PLA) devices. PALs and PLAs allow logic functions to be programmed by making or breaking connections between AND and OR gates. They provide a pre-fabricated structure of AND and OR gates that can be customized for an application. The document presents examples to illustrate how Boolean functions can be implemented using PALs and PLAs.

Uploaded by

Julia Daniel
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
43 views12 pages

Cs370 - Spring 2003 Programmable Logic Devices Pals/Plas

The document discusses Programmable Array Logic (PAL) and Programmable Logic Array (PLA) devices. PALs and PLAs allow logic functions to be programmed by making or breaking connections between AND and OR gates. They provide a pre-fabricated structure of AND and OR gates that can be customized for an application. The document presents examples to illustrate how Boolean functions can be implemented using PALs and PLAs.

Uploaded by

Julia Daniel
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 12

CS370 Spring 2003 Programmable Logic Devices PALs/PLAs

PALs and PLAs


Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

Inputs

Dens e array of AN D gates

Produc t terms

Dens e array of OR gates

Outputs

PALs and PLAs


Key to Success: Shared Product Terms Equations Example:

F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A


Input Side: 1 = asserted in term 0 = negated in term - = does not participate Output Side: 1 = term connected to output Reuse 0 = no connection to output of terms

Produc t Inputs Outputs term A B C F0 F1 F2 F3 0 1 1 0 AB 1 1 BC - 0 1 0 0 0 1 AC 1 - 0 0 1 0 0 BC - 0 0 1 0 1 0 1 0 0 1 A 1 - -

PALs and PLAs


Example Continued
A B C

All possible connections are available before programming

F0

F1

F2

F3

PALs and PLAs


Example Continued
A B C

Unwanted connections are "blown" AB /BC A /C /B /C A

Note: some array structures work by making connections rather than breaking them

F0

F1

F2

F3

PALs and PLAs


Alternative representation for high fan-in structures

Short-hand notation so that all the wires need not be drawn!

A B

C D

AB AB CD CD

Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

AB+AB CD + CD

PALs and PLAs


A B C
ABC A B C

Design Example

Multiple functions of A, B, C F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A xor B xor C F6 = A xnor B xnor C

A
B C ABC ABC ABC ABC ABC ABC ABC

F1

F2

F3

F4 F5

F6

PALs and PLAs


Difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA): PAL concept -- implemented by Monolithic Memories constrained topology of the OR Array I.e., the OR array cannot be fully programmed.

A given column of the OR array has access to only a subset of the possible product terms

PLA concept generalized topologies in AND and OR planes

PALs and PLAs


Design Example: BCD to Gray Code Converter
Truth Table
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 0 0 0 0 X X X X X X Y 0 0 1 1 1 1 1 1 0 0 X X X X X X Z 0 1 1 0 0 0 0 1 1 0 X X X X X X

K-maps
AB CD 00 01 11 C 10 0 1 B K-map f or W A 00 0 0 1 1 01 1 1 1 1 B K-map f or Y 11 X X X X 10 0 0 D 11 C 10 X X C 10 1 0 B K-map f or Z X X 11 0 1 X X X X 00 0 0 0 01 0 1 1 11 X X X A 10 1 1 D X C 10 0 0 B K-map f or X A 00 0 1 01 0 0 11 X X 10 1 0 D X X 11 0 0 X X AB CD 00 01 00 0 0 01 1 1 11 X X A 10 0 0 D

AB CD

AB CD 00 01

Minimized Functions: W=A+BD+BC X = B C' Y=B+C Z = A'B'C'D + B C D + A D' + B' C D'

00 01

PALs and PLAs


Programmed PAL:

A B C D A BD BC
0

BC
0 0 0

B C
0

0
ABCD

BCD AD BCD

4 product terms per each OR gate

PALs and PLAs


Code Converter Discrete Gate Implementation
A B D B C B C 1 \C 2 \B Y 2 2 1 1 \A \A \B \C D B C D A D X 1 \D \B C \D 1: 2,5: 3: 4: 3 3 4 4 5 Z

7404 hex inv erters 7400 quad 2-input NAN D 7410 tri 3-input NAND 7420 dual 4-input NAND

4 SSI Packages vs. 1 PLA/PAL Package!

PALs and PLAs


Example: Magnitude Comparator
AB CD 00 01 11 C 10 0 0 B K-map for EQ A 00 0 1 1 1 01 0 0 1 1 B K-map for LT 11 0 0 0 0 10 0 0 D 11 C 10 0 1 C 10 0 0 B K-map for GT 1 0 11 0 0 0 0 0 1 00 1 0 0 01 0 1 0 11 0 0 1 A 10 0 0 D 0 C 10 1 1 B K-map for NE 1 0 11 1 1 0 1 AB CD 00 01 00 0 1 01 1 0 11 1 1 A 10 1 1 D

C D ABCD ABCD ABCD ABCD AC AC BD BD

AB CD 00 01

AB CD 00 01 00 0 0 01 1 0 11 1 1

A 10 1 1 D

ABD
BCD ABC BCD

EQ NE LT

GT

You might also like