Verilog Tutorial

Chin-Lung Su

Laboratory for Reliable Computing (LaRC) Electrical Engineering Department

National Tsing Hua University

Outline
Introduction
Combinational Circuit
Programming style

How to program
Test-bench

Introduction
Hardware Description Language (HDL)
Verilog is useful and popular language Parallel not serial (Not like C language) Meaningful declaration
parameter, port name, module name,

Identifies
Even and even are different

Structure Programming

Module
Module is a block of circuit
Special function and, or, mux, adder,

Most important
Input and Output

Module

Flow
What functions are you want to program ?
Input and output

Separate the whole circuit into smaller ones

Each block has its own function / purpose

B1

B2

B3
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Scenario

Stimulus & Control Signal

Response & Verification

Test-Bench

Module

Monitor Signals

Verilog Model

Module Declaration
module module_name(input1, input2, , output1, output2, )
Example
module mux2(a, b, c);
module adder(x, y, z);

endmodule

Datatypes
Nests
Wire C[1:0] = {a,b}

Registers
reg

Integers
4d3, 4b0100, 6h20

Array
reg [9:0] ram

Parameter
parameter word_size = 16 wire [word_size-1:0] bus;

Preprocessor Directive
`define BEQ 4b0100

No =

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Synthesizable Description

`define
parameter wire always if/else

`include
input reg assign case/casex

module/endmodule
output begin/end posedge/negedge

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Un-synthesizable Description

Delay
forever join deassign primitive

initial
wait event force

Repeat
Foke Time Relace

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Synthesizable Operator
Binary Bitwise operator
~ &

|
^ ~^

inverse and or XOR XNOR

Example
Assign a=~b;
if b = 4b0010; then a = 4b1101;
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Logic
x y

y
0 1

z
1 0

x y x 0 0 1 1 y 0 1 0 1 z 0 0 0 1

x y x 0 0 1 1 y z

0 1 0 1

0 1 1 1
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Example
assign a=b & c
b = 4b0011 c = 4b0101
a = 4b0001

assgin a=b | c
b = 4b0011 c = 4b0101

a = 4b0111

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Program 1
Purpose
A circuit can calculate the addition and subtraction

of two 8 bits numbers Three inputs and one output

+ Mux s

op
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Program 1 (cont.)
/* A first program in Verilog */ module adder_or_subtract( a, b, op, s); parameter SIZE = 8; parameter ADD = 1b1; input op; input [SIZE-1:0] a,b; output [SIZE-1:0] s; a wire add, sub; assign add = a+b; b assign sub = a-b; assign s = (op==ADD)? add : sub; endmodule
comment

Model declaration

add

+ Mux sub op

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Program 1 (cont.)
module adder_or_subtract( a, b, op, s);
parameter parameter input input SIZE = 8; ADD = 1b1; op; [SIZE-1:0] a,b;

output

[SIZE-1:0] s;

assign s = (op==ADD)? A+b : a-b; endmodule

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Program 2
1-to-2 De-multiplexer

D Select 0 1 y0 D 0 y1 0 D

y0

y1

Select

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Program 2 (cont.)
/* A deMux program in Verilog */
module demux ( D, select, y0, y1); input D;
Model declaration comment

input
output wire assign assign

select;
y0,y1; y0,y1; y0 = (~select) & D; y1 = select & D;

endmodule
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Sub Module
Complex circuit
Many modules in a circuit Module, sub-module, sub-sub-module,

B1

B2

B3

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Example of Call Module

module B1(a, b, c);
.. endmodule

module B2(a, b, c, d);

.. endmodule module B3(x, y, z); ..
B1 B3 B2

endmodule
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Example of Call Module (cont.)

module function(q, w, e, f);
. B1 b1(q, w, a, b, c); B2 b2(a, b, d, e); B3 b3(c, d, f);
module B1(a, b, c); .. endmodule module B2(a, b, c, d); .. endmodule module B3(x, y, z); .. endmodule

endmodule

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Port Mapping Between Modules

# of ports need the same
Width of each port needs the same
module function(a,b,c,d); module B1(q, w, e, f);

.
B1 b1(w, q, a, c); endmodule

input q, w;
input [3:0] e; output [1:0] f; . endmodule

w q
a

q w
e

B1

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Port Mapping Between Modules (cont.)

Port name should match the name in sub_module
Prot connection
module_name( .port1_m1(w1_or_r1),

.port2_m1(w2_or_r2), .port3_m1(w3_or_r3), .port4_m1(w4_or_r4),

) module_name( .port3_m1(w3_or_r3), .port2_m1(w2_or_r2), .port1_m1(w1_or_r1), .port4_m1(w4_or_r4), )
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Connection Between Modules (cont.)

Prot connection
module function(a,b,c,d); B1 b1(q, w, a, c); B1 b1(.q(q), .w(w), .e(a), .f(c)) B1 b1(.w(w), .q(q), .e(a), .f(c)) endmodule module B1(q, w, e, f); input q, w; input [3:0] e;
q
w a

q
w e

B1

output [1:0] f;
. endmodule
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Reuse Module
Using the same module many times
Example
Constructing 4-bits adder with four 1-bit adder

b3 a3

b2 a2

b1 a1

b0 a0

c3

c2

c1

s4

s3

s2

s1

s0

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4-bists Adder
module Adder(x, y, cin, sum, cout);
input x, y, c; output sum, cout; wire x, y, c, sum, cout; assign sum = x ^ y ^ cin;
cout y x

cin

sum

assign cout = (x & y) | (x & cin) | (y & cin);

assign {cout, sum} = x + y + cin;

endmodule

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4-bists Adder (cont.)

module Adder4(x, y, cin, sum);

input [3:0]x, y input cin; output [4:0]sum; wire [3:0] x, y; wire [4:0] sum; wire c1, c2, c3; wire cin; s4

b3 a3

b2 a2

b1 a1

b0 a0 cin

c3

c2

c1

s3

s2

s1

s0

Adder A1(x[0], y[0], cin, sum[0], c1);

Adder A2(x[1], y[1], c1, sum[1], c2); Adder A3(x[2], y[2], c2, sum[2], c3); Adder A4(x[3], y[3], c3, sum[3], sum[4]); endmodule
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Mistake
module and endmodule
module();Module(); (;) port bus

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Always Block
Syntax
always @(event-expression)

assignment or block

Level type
always @(a or b or c)

Edge type
always @(posedge clock) always @(negedge clock)

if-else and case statement are only in always block wire and reg
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Example
wire a;
reg b; always @(x or y or z) begin a <= x & y;

error
correct

b <= x | z;
end

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Program 2 (cont.)
/* A deMux program in Verilog */
module demux ( D, select, y0, y1); input output y0,y1; D, select;

reg

y0,y1;
D y0

always @( D or select ) begin if( select == 1b0)begin y0 = D; end else begin y0 = 1b0; y1 = D; y1 = 1b0;

y1

end
end endmodule
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Select

Blocking and Non-blocking

Symbol
Blocking Non-blocking

= <=
A <= B B <= A

A=B B=A

A A B

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Blocking and Non-blocking

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if statement
Like C language
Only in always block

reg out; always @(sel or a or b) begin if(sel == 1b1) out = a; else out = b; end

wire out; assign out = (sel)? a : b;

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Using of case and casex

Multiplexer or selection
Inside always block All possible condition
always @(sel or a or b or c or d) begin case (sel[1:0] ) 2b00 : out <= a; 2b01 : out <= b; 2b10 : out <= c; 2b11 : out <= d; endcase end
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a b c d Sel [1:0] out

Using of case and casex (cont.)

a b c out

Sel [1:0]

always @(sel or a or b or c or d) begin case (sel[1:0] ) 2b00, 2b11 : out <= a; 2b01 : out <= b; 2b10 : out <= c; endcase end

a b out

c
d

Sel [2:0]

always @(sel or a or b or c or d) begin casex (sel[2:0] ) 3b011 : out <= a; 3b00x : out <= b; 3b100 : out <= c; default : out <= d; endcasex All others end

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Delay and Critical Path

Each gate and wire may cause delay of circuit
Longest path of the circuit is critical path
Speed of whole circuit

Shorten the critical path can speedup the circuit

Input data rate higher than the speed of circuit may cause some problems

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Critical Path Example

5 inputs adder
Z=a+b+c+d+e
a b
a + b c d

Z = (a + b) + (c + d) + e

c +
+ d +

+ Three adders
e

Four adders
e

+
+ Z Z
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Test-bench
Input data of the circuit
All inputs of original circuit are assigned reg
Store data

All outputs of original circuit are assigned wire

Assign inputs in different time Define time scale

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Test-bench Example
`timescale 1ns/100fs
module Adder_testbench; reg [3:0] x,y; reg cin; wire [4:0] sum;
Initialization

adder4 add(.x(x), .y(y), .cin(cin), .sum(sum));

initial begin #0 #10 #5 #10 end
module Adder4(x, y, cin, sum);
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x = 4d0; x = 4d3; y = 4d10; x = 4d1;

y = 4d0;

cin=1b0;
InIn 10ns 25ns x=3; x=1; y=0; y=5; In 15ns sum=3; x=3; sum=6; y=10; sum=13;

y = 4d5;

endmodule