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Vlsi Test Process & Ecconomics

brief description on vlsi realization process

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82 views

Vlsi Test Process & Ecconomics

brief description on vlsi realization process

Uploaded by

reneeshcz
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Lecture 1 Introduction

VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device - system-on-a-chip Course outline Part I: Introduction to testing Part II: Test methods Part III: Design for testability
VLSI Test: Lecture 1 1

Copyright 2001, Agrawal & Bushnell

VLSI Realization Process


Customers need
Determine requirements

Write specifications
Design synthesis and Verification

Test development
Fabrication Manufacturing test

Chips to customer
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 1 2

Definitions

Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

Verification vs. Test


Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.

Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.
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Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

Problems of Ideal Tests


Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open

problem.

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

Real Tests

Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

Testing as Filter Process


Good chips Prob(pass test) = high Prob(good) = y Fabricated chips Defective chips Prob(bad) = 1- y Prob(fail test) = high Mostly bad chips
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Mostly good chips

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

Costs of Testing

Design for testability (DFT)


Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

Design for Testability (DFT)


DFT refers to hardware design styles or added hardware that reduces test generation complexity.
Motivation: Test generation complexity increases exponentially with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. Logic bus Logic PO PI block A block B Test input
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 1

Test output
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Present and Future*


1997 -2001 2003 - 2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10 Transistors/sq. cm 4 - 10M 18 - 39M

Pin count Clock rate (MHz) Power (Watts)

100 - 900 200 - 730 1.2 - 61

160 - 1475 530 - 1100 2 - 96

* SIA Roadmap, IEEE Spectrum, July 1999


Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 1 10

Cost of Manufacturing Testing in 2000AD

0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second
VLSI Test: Lecture 1 11

Copyright 2001, Agrawal & Bushnell

Roles of Testing

Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

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A Modern VLSI Device System-on-a-chip (SOC)


Data terminal

DSP cor e Interface logic

RAM ROM Mixedsignal Codec

Transmission medium

Figure 18.5 (page 605)


Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 1 13

Course Outline Part I: Introduction


Basic concepts and definitions (Chapter 1) Test process and ATE (Chapter 2) Test economics and product quality (Chapter 3) Fault modeling (Chapter 4)

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Course Outline (Cont.) Part II: Test Methods


Logic and fault simulation (Chapter 5) Testability measures (Chapter 6) Combinational circuit ATPG (Chapter 7) Sequential circuit ATPG (Chapter 8) Memory test (Chapter 9) Analog test (Chapters 10 and 11) Delay test and IDDQ test (Chapters 12 and 13)

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Course Outline (Cont.) Part III: DFT


Scan design (Chapter 14) BIST (Chapter 15) Boundary scan and analog test bus (Chapters 16 and 17) System test and core-based design (Chapter 18)

Copyright 2001, Agrawal & Bushnell

VLSI Test: Lecture 1

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