Figure 3­1      Example truth tables for (a) two­input, (b) three­input, and (c) four­input circuits.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­2      (a) Truth table defining the OR operation; (b) circuit symbol for a two­input OR gate.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­3      Symbol and truth table for a three­input OR gate.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­4      Example of the use of an OR gate in an alarm system.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­5      Example 3­2.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­6      Examples 3­3A and B.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­7      (a) Truth table for the AND operation; (b) AND gate symbol.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­8      Truth table and symbol for a three­input AND gate.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­9      Example 3­4.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­10      Examples 3­5A and B.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­11      (a) Truth table; (b) symbol for the INVERTER (NOT circuit); (c) sample waveforms.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­12      A NOT gate indicating a button is not pressed when its output is true.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­13      (a) Logic circuit with its Boolean expression; (b) logic circuit whose expression requires parentheses.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­13 (continued)      (a) Logic circuit with its Boolean expression; (b) logic circuit whose expression requires parentheses.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­14      Circuits using INVERTERs.

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Figure 3­15      More examples.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­16      Analysis of a logic circuit using truth tables.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­17      Constructing a logic circuit from a Boolean expression.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­18      Example 3­7.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­19      (a) NOR symbol; (b) equivalent circuit; (c) truth table.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­20      Example 3­8.     

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­21      Example 3­9.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­22      (a) NAND symbol; (b) equivalent circuit; (c) truth table.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­23      Example 3­10.

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Figure 3­24      Examples 3­11 and 3­12.

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Figure 3­25      Single­variable theorems.

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Figure 3­26      (a) Equivalent circuits implied by theorem (16); (b) alternative symbol for the NOR function.

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Figure 3­27      (a) Equivalent circuits implied by theorem (17); (b) alternative symbol for the NAND function.

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Figure 3­28      Example 3­17.     

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Figure 3­29      NAND gates can be used to implement any Boolean function.

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Figure 3­30      NOR gates can be used to implement any Boolean operation.

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Figure 3­31      ICs available for Example 3­18.

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Figure 3­32      Possible implementations for Example 3­18.

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Figure 3­33      Standard and alternate symbols for various logic gates and inverter.

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Figure 3­34      Interpretation of the two NAND gate symbols.

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Figure 3­35      Interpretation of the two OR gate symbols.

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Figure 3­36      (a) Original circuit using standard NAND symbols; (b) equivalent representation where output Z is active­HIGH; (c) 
equivalent representation where output Z is active­LOW; (d) truth table.

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Figure 3­37      Example 3­20.

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Figure 3­38      Example 3­21.

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Figure 3­39      Example 3­22.

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Figure 3­40      Example 3­23.

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Figure 3­41      Standard logic symbols: (a) traditional; (b) IEEE/ANSI.

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­42      Methods of describing logic circuits: (a) Boolean expression; (b) schematic diagram; (c) truth table; (d) timing diagram.

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Figure 3­43      Decision process of a computer program.

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Figure 3­44      Configuring hardware connections with programmable logic devices.

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Figure 3­45      A schematic diagram description.

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Figure 3­46      Format of HDL files.

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Figure 3­47      Essential elements in AHDL.

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Figure 3­48      Essential elements in VHDL.

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Figure 3­49      A logic circuit diagram with an intermediate variable.

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Figure 3­50      Intermediate variables in AHDL described in Figure 3­49.

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Figure 3­51      Intermediate signals in VHDL described in Figure 3­49.

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Figure 3­52      

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Figure 3­53      

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Figure 3­54      

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Figure 3­55      

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Figure 3­56      

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­57      

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By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 3­58       

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
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