William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory

Semiconductor Memory Types

Memory Type Category Erasure Write Mechanism Volatility

Random-access memory (RAM)

Read-write memory

Electrically, byte-level

Electrically

Volatile

Read-only memory (ROM) Read-only memory Programmable ROM (PROM) Erasable PROM (EPROM) Not possible

Masks

UV light, chip-level Electrically

Nonvolatile

Electrically Erasable PROM (EEPROM)

Read-mostly memory

Electrically, byte-level

Flash memory

Electrically, block-level

Semiconductor Memory
RAM
Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic

Memory Cell Operation

Dynamic RAM
Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue
Level of charge determines value

Dynamic RAM Structure

DRAM Operation
Address line active when bit read or written
Transistor switch closed (current flows)

Write
Voltage to bit line
High for 1 low for 0

Then signal address line

Transfers charge to capacitor

Read
Address line selected
transistor turns on

Charge from capacitor fed via bit line to sense amplifier

Compares with reference value to determine 0 or 1

Capacitor charge must be restored

Static RAM
Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital
Uses flip-flops

Stating RAM Structure

Static RAM Operation

Transistor arrangement gives stable logic state State 1 State 0
C1 high, C2 low T1 T4 off, T2 T3 on C2 high, C1 low T2 T3 off, T1 T4 on

Address line transistors T5 T6 is switch Write apply value to B & compliment to B Read value is on line B

SRAM v DRAM
Both volatile
Power needed to preserve data

Dynamic cell
Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units

Static
Faster Cache

Read Only Memory (ROM)

Permanent storage
Nonvolatile

Microprogramming (see later) Library subroutines Systems programs (BIOS) Function tables

Summary
Read-Only Memory (ROM) A ROM symbol is shown with typical inputs and outputs. The triangles on the outputs indicate it is a tri-stated device.
To read a value from the ROM, an address is placed on the address bus, the chip is enabled, and a short time later (called the access time), data appears on the data bus.
Address transition Address input lines Valid address on input lines ta Data outputs Valid data on output lines Data output transition Chip select Address input lines A0 A1
D ROM 2564 0

Data output lines

0

A3

A6 A7 E0 E1

7 & EN

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A5

A4

A 255

A2

O0 O1 O2 O3

Types of ROM
Written during manufacture
Very expensive for small runs

Programmable (once)
PROM Needs special equipment to program

Read mostly
Erasable Programmable (EPROM)
Erased by UV

Electrically Erasable (EEPROM)

Takes much longer to write than read

Flash memory
Erase whole memory electrically

Summary
Flash Memory Flash memories are high density read/write memories that are nonvolatile. They have the ability to retain charge for years with no applied power.
Floating gate Drain

Flash memory uses a MOS transistor with a floating gate as the basic storage cell. The floating gate can store charge (logic 0) when a positive voltage is applied to the control gate. With little or no charge, the cell stores a logic 1.

Control gate

MOS transistor symbol

Source

logic 0 is stored

logic 1 is stored

The flash memory cell can be read by applying a positive voltage to the control gate. If the cell is storing a 1, the positive voltage is sufficient to turn on the transistor; if it is storing a 0, the transistor is off.
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Summary
Flash Memory Flash memories arranged in arrays with an active load. For simplicity, only one column is shown. When a specific row and column is selected during a read operation, the active load has current.
One drawback to flash memory is that once a bit has been set to 0, it can be reset to a 1 only by erasing an entire block of memory. Another limitation is that flash memory has a large but finite number of read/write cycles.
Floyd, Digital Fundamentals, 10th ed
+V Active load

Comparator Bit line 0 Reference

Data out 0

Row select 0

Row select 1

Row select n

Column select 0

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Memory Expansion Memory can be expanded in either word size or word capacity or both. To expand word size:
Address bus

RAM 2m 2n
m bits

Data in/out Control bus

n bits

Data in/out

2n bits Data bus

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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Notice that the data bus size is larger, but the number of address is the same.

m bits

RAM 1 2m n

m bits

RAM 2 2m n

n bits

Memory Expansion To expand word capacity, Address you need to add an address 21 bus bits line as shown in this example
Control bus RAM 2M 8 20 bits RAM 1 1M 8 EN 8 bits

Notice that the data bus size does not change.

8 bits Data bus 20 bits RAM 2 1M 8 EN 8 bits

What is the purpose of the inverter?

Floyd, Digital Fundamentals, 10th ed

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Organisation in detail
A 16Mbit chip can be organised as 1M of 16 bit words A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
Reduces number of address pins
Multiplex row address and column address 11 pins to address (211=2048) Adding one more pin doubles range of values so x4 capacity

Refreshing
Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance

Typical 16 Mb DRAM (4M x 4)

Packaging

256kByte Module Organisation

1MByte Module Organisation

Interleaved Memory
Collection of DRAM chips Grouped into memory bank Banks independently service read or write requests K banks can service k requests simultaneously

Error Correction
Hard Failure
Permanent defect

Soft Error
Random, non-destructive No permanent damage to memory

Detected using Hamming error correcting code

Error Correcting Code Function

Hamming Code Syndrome If we compare the read K bits compared with the write K bits, using an EXOR function, the result is called the syndrome.
If the syndrome is all zeros, there were no errors. If there is a 1 bit somewhere, we know it represents an error.

Hamming Code Design determining K

To store an M bit word with detection/correction takes M+K bit words If K =1, we can detect single bit errors but not correct them If 2K - 1 >= M + K , we can detect, identify, and correct all single bit errors, i.e. the syndrome contains the information to correct any single bit error

Example: For M = 8:

and K = 3: 23 1 = 7 < 8 + 3 (doesnt work) and K = 4: 24 1 = 15 > 8 + 4 (works!) Therefore, we must choose K =4, i.e., the minimum size of the syndrome is 4

Increased word length for error correcting

Hamming Code Syndrome Design Criteria

A Layout of Data and Check Bits that Achieves Our Design Criteria:

Bit position Bit number Data bit Check bit

12 1100 D8

11 1011 D7

10 1010 D6

9 1001 D5

8 1000 C8

7 0111 D4

6 0110 D3

5 0101 D2

4 0100 C4

3 0011 D1

2 0010 C2

1 0001 C1

C1 is a parity check on every data bit whose position is xxx1

C1 = D1 exor D2 exor D4 exor D5 exor D7

C2 is a parity check on every data bit whose position is xx1x

C2 = D1 exor D3 exor D4 exor D6 exor D7

C4 is a parity check on every data bit whose position is x1xx

C4 = D2 exor D3 exor D4 exor D8

C8 is a parity check on every data bit whose position is 1xxx

C8 = D5 exor D6 exor D7 exor D8

Why this ordering? Because we want the syndrome, the Hamming test word, to yield the address of the error.

Example:
Data stored = 00111001
Check bits:

Putting it together:

Example:

Example:
Word fetched:

Check Bits:

Comparing:
C8 C4 C2 C1 0 1 0 1 1 1 Orig Check Bits 1 0 Syndrome 0 0 0 1 New Check Bits

Putting it all together:

0110 = 6 bit position 6 is wrong, i.e. bit D3 is wrong

Increased word length for error correcting

SEC-DEC Example Requires One Extra Check Bit

Single Error Correction:
Word With Even Parity

Single Error Correction, Double Error Detection:

Word With Even Parity With Two Errors

With Errors

Identifying Error

SEC Attempt

IS SEC Correct?

Extra Bit Confirms DE

Increased word length for error correcting

Advanced DRAM Organization

Basic DRAM same since first RAM chips Enhanced DRAM
Contains small SRAM as well SRAM holds last line read (c.f. Cache!)

Cache DRAM
Larger SRAM component Use as cache or serial buffer

Synchronous DRAM (SDRAM)

Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

SDRAM

SDRAM Read Timing

RAMBUS
Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps Asynchronous block protocol
480ns access time Then 1.6 Gbps

RAMBUS Diagram

DDR SDRAM
SDRAM can only send data once per clock Double-data-rate SDRAM can send data twice per clock cycle
Rising edge and falling edge

DDR SDRAM Read Timing

Simplified DRAM Read Timing

Cache DRAM
Mitsubishi Integrates small SRAM cache (16 kb) onto generic DRAM chip Used as true cache
64-bit lines Effective for ordinary random access

To support serial access of block of data

E.g. refresh bit-mapped screen
CDRAM can prefetch data from DRAM into SRAM buffer Subsequent accesses solely to SRAM

Reading
The RAM Guide RDRAM

 Consider a dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns; a memory cycle requires 250 ns.What percentage of the memorys total operating time must be given to refreshes?

1. Static RAM is

a. nonvolatile read only memory

b. nonvolatile read/write memory c. volatile read only memory d. volatile read/write memory

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2. A nonvolatile memory is one that

a. requires a clock
b. must be refreshed regularly c. retains data without power applied d. all of the above

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3. The advantage of dynamic RAM over static RAM is that

a. it is much faster
b. it does not require refreshing c. it is simpler and cheaper d. all of the above

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4. The first step in a read or write operation for a random access memory is to a. place a valid address on the address bus b. enable the memory

c. send or obtain the data

d. start a refresh cycle

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5. The output enable signal (OE) on a RAM is active a. only during a write operation b. only during a read operation

c. both of the above

d. none of the above

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6. When data is read from RAM, the memory location is

a. cleared after the read operation

b. set to all 1s after the read operation c. unchanged d. destroyed

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7. An EPROM has a window to allow UV light to enter under certain conditions. The purpose of this is to a. refresh the data b. read the data

c. program the IC
d. erase the data

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8. The small triangles on the logic diagram indicate that these outputs are a. not used b. tri-stated
Address input lines A0 A1
D ROM 2564 0

Data output lines

0

A3

A6 A7 E0 E1

7 & EN

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d. grounded

A5

A4

A 255

c. inverted

A2

O0 O1 O2 O3

9. Using two ICs as shown will expand a. the word size b. the number of words available c. both of the above d. none of the above
Address bus

RAM 2m 2n
m bits

m bits

RAM 1 2m n

m bits

RAM 2 2m n

Data in/out Control bus

n bits

Data in/out

2n bits Data bus

D n bits

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10. On a hard drive. information about file names, locations, and file size are kept in a special location called the a. file location list b. file allocation table

c. disk directory
d. stack

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