Datapaths

For the rest of the semester, well focus on computer architecture: how to assemble the combinational and sequential components weve studied so far into a complete computer. Today, well start with the datapath, the part of the central processing unit (CPU) that does the actual computations.

Datapaths

Keep it simple!
Abstraction is very helpful in understanding processors. Although we studied how devices like registers and muxes are built,

we dont need that level of detail here. You should focus more on what these component devices are doing, and less on how they work. Otherwise its easy to get bogged down in the details, and datapath and control units can be a little intimidating.

Datapaths

An overview of CPU design

We can divide the design of our CPU into three parts: The datapath does all of the actual data processing. An instruction set is the programmers interface to CPU. A control unit uses the programmers instructions to tell the datapath what to do. Today well look in detail at a processors datapath, which is responsible for doing all of the dirty work. An ALU does computations, as weve seen before. A limited set of registers serves as fast temporary storage. A larger, but slower, random-access memory is also available.

Datapaths

Whats in a CPU?
ALU

Registers

A processor is just one big sequential circuit. Some registers are used to store values, which form the state. An ALU performs various operations on the data stored in the registers.

Datapaths

Register transfers
ALU

Registers

Fundamentally, the processor is just moving data between registers, possibly with some ALU computations. To describe this data movement more precisely, well introduce a register transfer language. The objects in the language are registers. The basic operations are transfers, where data is copied from one register to another. We can also use the ALU to perform arithmetic operations on the data while were transferring it.

Datapaths

Register transfer language

Two-character names denote registers, such as R0, R1, DR, or SA. Arrows indicate data transfers. To copy the contents of the source register R2 into the destination register R1 in one clock cycle:

R1 R2

A conditional transfer is performed only if the Boolean condition in front of the colon is true. To transfer R3 to R2 when K = 1:

K: R2 R3

Multiple transfers on the same clock cycle are separated by commas. R1 R2, K: R2 R3

Dont confuse this register transfer language with assembly language, which well discuss next week.
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Register transfer operations

We can apply arithmetic operations to registers. R1 R2 + R3 R3 R1 - 1

Logical operations are applied bitwise. AND and OR are denoted with special symbols, to prevent confusion with arithmetic operations. R2 R1 R2 bitwise AND

R3 R0 R1

bitwise OR

Lastly, we can shift registers. Here, the source register R1 is not modified, and we assume that the shift input is just 0.

R2 sl R1 R2 sr R1

left shift right shift

Datapaths

Block symbols for registers

Load Data input Data output

n n
R0

Well use this block diagram to represent an n-bit register. There is a data input and a load input. When Load = 1, the data input is stored into the register. When Load = 0, the register will keep its current value. The registers contents are always available on the output lines, regardless of the Load input. The clock signal is not shown because it would make the diagram messy. Remember that the input and output lines are actually n bits wide!

Datapaths

A better parallel load

Another idea is to modify the flip-flop D inputs and not the clock signal. When LD = 0, the flip-flop inputs are Q3-Q0, so each flip-flop just keeps its current value. When LD = 1, the flip-flop inputs are D3-D0, and this new value is loaded into the register.

Datapaths

Register files

Modern processors contain a number of registers grouped together in a register file. Much like words stored in a RAM, individual registers are identified by an address. Here is a block symbol for a 2k x n register file. There are 2k registers, so register addresses are k bits long. Each register holds an nbit word, so the data inputs and outputs are n bits wide.
D n D data WR DA k Write D address Register File AA k A address A data n A B address B data n B k BA

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Accessing the register file

You can read two registers at once by supplying the AA and BA inputs. The data appears on the A and B outputs. You can write to a register by using the DA and D inputs, and setting WR = 1. These are registers so there must be a clock signal, even though we usually dont show it in diagrams. We can read from the register file at any time. Data is written only on the positive edge of the clock.
D n D data WR DA k Write D address Register File AA k A address A data n B address B data n k BA

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Whats inside the register file

Heres a 4 x n register file. (Well assume a 4 x n register file for all our examples.)
n

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Whats inside the register file

Heres a 4 x n register file. (Well assume a 4 x n register file for all our examples.)

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Explaining the register file

The 2-to-4 decoder selects one of the four registers for writing. If WR = 1, the decoder will be enabled and one of the Load signals will be active. The n-bit 4-to-1 muxes select the two register file outputs A and B, based on the inputs AA and BA. We need to be able to read two registers at once because most arithmetic operations require two operands.

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The all-important ALU

The main job of a central processing unit is to process, or to perform computations....remember the ALU from way back when? Well use the following general block symbol for the ALU. A and B are two n-bit numeric inputs. FS is an m-bit function select code, which picks one of 2m functions. The n-bit result is called F. Several status bits provide more n n information about the output F: V = 1 in case of signed overflow. A B C is the carry out. m FS N = 1 if the result is negative. ALU V Z = 1 if the result is 0. C N This should all look familiar from previous Z homeworks! F
n

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ALU functions

For concrete examples, well use the ALU as its presented in the textbook. The table of operations on the right is taken from page 457. The function select code FS is 4 bits long, but there are only 15 different functions here. We use an alternative notation for AND and OR to avoid confusion with arithmetic operations.
FS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 F F F F F F F F = = = = = = = = Operation A A+1 A+B A+B+1 A + B' A + B' + 1 A-1 A

B (AND) F = A B (OR)
F=A F F F F F = = = = = A B (XOR) A' B sr B (shift right) sl B (shift left)

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My first datapath

Here is the most basic datapath. The ALUs two data inputs come from the register file. The ALU computes a result, which is saved back to the registers. WR, DA, AA, BA and FS are control signals. Their values determine the exact actions taken by the datapath which registers are used and for what operation. Remember that many of the signals here are actually multi-bit values.
D data WR DA 2 Write D address Register File AA 2 A address A data n A FS 4 FS V C N Z ALU B address 2 B data n B BA

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An example computation

Lets look at the proper control signals for the operation below: R0 R1 + R3
D data Write D address Register File AA 01 A address A data B address B data BA 11

Set AA = 01 and BA = 11. This causes the contents of R1 to appear at A data, and the contents of R3 to appear at B data. Set the ALUs function select input FS = 0010 (A + B). Set DA = 00 and WR = 1. On the next positive clock edge, the ALU result (R1 + R3) will be stored in R0.

WR 1 DA 00

A FS 0010 FS V C N Z ALU

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Two questions

Four registers isnt a lot. What if we need more storage? Who exactly decides which registers are read and written and which ALU function is executed?
D data WR DA Write D address Register File AA A address A data B address B data BA

A FS FS V C N Z ALU

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We can access RAM also

Heres a way to connect RAM into our existing datapath. To write to RAM, we must give an address and a data value. These will come from the registers. We connect A data to the memorys ADRS input, and B data to the memorys DATA input. Set MW = 1 to write to the RAM. (Its called MW to distinguish it from the WR write signal on the register file.)
n D data Write D address

WR DA

Register File
AA A address B address A data n B data n BA RAM ADRS DATA OUT CS WR

FS

FS V C N Z

A
ALU F n

+5V MW 1

D0 Q D1 S

n MD

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Reading from RAM

To read from RAM, A data must supply the address. Set MW = 0 for reading. The incoming data will be sent to the register file for storage. This means that the register files D data input could come from either the ALU output or the RAM. A mux MD selects the source for the register file. When MD = 0, the ALU output can be stored in the register file. When MD = 1, the RAM output is sent to the register file instead.
n D data Write D address

WR DA

Register File
AA A address B address A data n B data n BA RAM ADRS DATA OUT CS WR

FS

FS V C N Z

A
ALU F n

+5V MW 0

D0 Q D1 S

n MD

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Notes about this setup

We now have a way to copy data between our register file and the RAM. Notice that theres no way for the ALU to directly access the memoryRAM contents must go through the register file first. Here the size of the memory is limited by the size of the registers; with n-bit registers, we can only use a 2n x n RAM. For simplicity well assume the RAM is at least as fast as the CPU clock. (This is definitely not the case in real processors these days.)
n D data Write D address

WR DA

Register File
AA A address B address A data n B data n BA RAM ADRS DATA OUT CS WR

FS

FS V C N Z

A
ALU F n

+5V MW

D0 Q D1 S

n MD

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Memory transfer notation

In our transfer language, the contents at random access memory address X are denoted M[X]. For example: The first word in RAM is M[0]. If register R1 contains an address, then M[R1] are the contents of that address. The M[ ] notation is like a pointer dereference operation in C or C++.

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Example sequence of operations

Here is a simple series of register transfer instructions: R3 M[R0] R3 R3 + 1 M[R0] R3

This just increments the contents at address R0 in RAM. Again, our ALU only operates on registers, so the RAM contents must first be loaded into a register, and then saved back to RAM. R0 is the first register in our register file. Well assume it contains a valid memory address. How would these instructions execute in our datapath?

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R3 M[R0]

AA should be set to 00, to read register R0. The value in R0 will be sent to the RAM address input, so M[R0] appears as the RAM output OUT. MD must be 1, so the RAM output goes to the register file. To store something into R3, well need to set DA = 11 and WR = 1. MW should be 0, so nothing is accidentally changed in RAM. Here, we did not use the ALU (FS) or the second register file output (BA).
n 1 WR DA 11 AA 00 D data Write D address

Register File
A address B address A data n B data n BA RAM ADRS DATA OUT CS WR

FS

FS V C N Z

A
ALU F n

+5V MW 0

D0 Q D1 S

n MD 1

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R3 R3 + 1

AA = 11, so R3 is read from the register file and sent to the ALUs A input. FS needs to be 0001 for the operation A + 1. Then, R3 + 1 appears as the ALU output F. If MD is set to 0, this output will go back to the register file. To write to R3, we need to make DA = 11 and WR = 1. Again, MW should be 0 so the RAM isnt inadvertently changed. We didnt use BA.
n 1 WR DA 11 AA 11 D data Write D address

Register File
A address B address A data n B data n BA RAM ADRS DATA OUT CS WR

0001 FS

FS V C N Z

A
ALU F n

+5V MW 0

D0 Q D1 S

n MD 0

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M[R0] R3

Finally, we want to store the contents of R3 into RAM address R0. Remember the RAM address comes from A data, and the contents come from B data. So we have to set AA = 00 and BA = 11. This sends R0 to ADRS, and R3 to DATA. MW must be 1 to write to memory. No register updates are needed, so WR should be 0, and MD and DA are unused. We also didnt use the ALU, so FS was ignored.
n 0 WR DA D data Write D address

Register File
AA 00 A address B address A data n B data n BA 11 RAM ADRS DATA OUT CS WR

FS

FS V C N Z

A
ALU F n

+5V MW 1

D0 Q D1 S

n MD

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Constant in

One last refinement is the addition of a Constant input. The modified datapath is shown on the right, with one extra control signal MB. Well see how this is used later. Intuitively, it provides an easy way to initialize a register or memory location with some arbitrary number.
WR DA D data Write D address Register File A address B address A data Constant MB S D1 D0 Q +5V MW RAM ADRS DATA CS WR OUT B data BA

AA

FS

FS V C N Z

A ALU F

D0 Q D1 S

MD

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Control units

From these examples, you can see that different actions are performed when we provide different inputs for the datapath control signals. The second question we had was Who exactly decides which registers are read and written and which ALU function is executed? In real computers, the datapath actions are determined by the program thats loaded and running. A control unit is responsible for generating the correct control signals for a datapath, based on the program code. Well talk about programs and control units next week.

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Summary

The datapath is the part of a processor where computation is done. The basic components are an ALU, a register file and some RAM. The ALU does all of the computations, while the register file and RAM provide storage for the ALUs operands and results. Various control signals in the datapath govern its behavior. Next week, well see how programmers can give commands to the processor, and how those commands are translated in control signals for the datapath.

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