Fundamental Concepts of BPU

Fundamental Concepts
Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). Instruction Register (IR)
Executing an Instruction
Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR [[PC]] Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC [PC] + 4 Carry out the actions specified by the instruction in the IR (execution phase).
Internal processor bus Control signals PC Instruction Address lines MAR Memory bus MDR Data lines IR decoder and control logic
Y Constant 4 R0
Select
MUX Add
ALU control lines
Sub
A ALU
R n - 1
Carry -in XOR Z TEMP
Processor Organization
Figure 7.1. Single-bus organization of the datapath inside a processor.
Datapath
Executing an Instruction
Transfer a word of data from one processor register to another or to the ALU. Perform an arithmetic or a logic operation and store the result in a processor register. Fetch the contents of a given memory location and load them into a processor register. Store a word of data from a processor register into a given memory location.
Bus
0 D 1 Q Ri in Riout Q
Clock
Figure 7.3. Input and output ating g for one gister re bit.
Register Transfers
All operations and data transfers are controlled by the processor clock.
Input and output gating for one register bit.
Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no internal storage. ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z. What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?
1. 2.
3.
R1out, Yin R2out, SelectY, Add, Zin Zout, R3in
Memory -b us data lines
MDRoutE
MDRout
Internal processor bus
MDR
Fetching a Word from Memory

Figure 7.4. Connection and control signals for gister re MDR.
MDR inE
MDRin
Address into MAR; issue Read operation; data into MDR.
Connection and control signals for register MDR.
Fetching a Word from Memory

The response time of each memory access varies (cache miss, memory-mapped I/O,). To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC). Move (R1), R2
MAR [R1] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus R2 [MDR]
Execution of a Complete Instruction

Add (R3), R1 Fetch the instruction Fetch the first operand (the contents of the memory location pointed to by R3) Perform the addition Load the result into R1
Step 1 2 3 4 5 6 7
Action
PCout , MAR in , Read, Select4, A dd, Zin Zout , PCin , Y in , WMF C MDR out , IR in
PC
Control signals
Figure 7.6. Control sequence for executionof the instruction Add (R3),R1.

Instruction
R3out , MAR in , Read R1out , Y in , WMF C
Address lines
decoder and
MAR
control logic
Memory bus
MDR out , SelectY,Add, Zin Zout , R1 in , End
MDR
Data lines
IR
Constant 4
R0
Select
MUX
Add
ALU control lines
Sub
R n - 1
ALU
Carry -in
XOR
TEMP
Add (R3), R1
Add R2, R1 ?
Step 1 2 3 4 5 6 7
Action
PCout , MAR in , Read, Select4, A dd, Zin Zout , PCin , Y in , WMF C MDR out , IR in
PC
Control signals
Figure 7.6. Control sequence for executionof the instruction Add (R3),R1.

Instruction
R3out , MAR in , Read R1out , Y in , WMF C
Address lines
decoder and
MAR
control logic
Memory bus
MDR out , SelectY,Add, Zin Zout , R1 in , End
MDR
Data lines
IR
Constant 4
R0
Select
MUX
Add
ALU control lines
Sub
R n - 1
ALU
Carry -in
XOR
TEMP
Add R2, R1
R2out
Execution of Branch Instructions
A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction. The offset X is usually the difference between the branch target address and the address immediately following the branch instruction. Conditional branch
Execution of Branch Instructions

Step Action
1 2 PCout , MAR in , Read, Select4,Add, Z in Zout , PCin , Yin , WMF C
3
4 5
MDR out , IR in
Offset-field-of-IR out, Add, Z in Z out , PCin , End
Control sequence for an unconditional branch instruction.
Bus A
Bus B
Incrementer
Bus C
PC
Re gister f ile
Constant 4
MUX
A ALU B R
Instruction decoder
IR
Multiple-Bus Organization
MDR MAR Memory b us data lines Address lines
Figure 7.8. T hree-b us or ganization of the datapath.
Allow the contents of two different registers to be accessed simultaneously and have their contents placed on buses A and B. Allow the data on bus C to be loaded into a third register during the same clock cycle. Incrementer unit.
ALU simply passes one of ts two input operands unmodified to bus C

control signal: R=A or R=B
Multiple-Bus Organization
Add R4, R5, R6
Step Action 1 2 3 4 PCout, R=B, MAR in , Read, IncPC WMFC MDR outB , R=B, IR in R4outA , R5outB , SelectA, Add, R6in , End
Control sequence for the instruction. Add R4,R5,R6, for the three-bus organization
Internal processor bus Control signals PC Instruction Address lines MAR Memory bus MDR Data lines IR decoder and control logic
Y Constant 4 R0
Select
MUX Add
ALU control lines
Sub
A ALU
R n - 1
Carry -in XOR Z TEMP
Exercise
What is the control sequence for execution of the instruction Add R1, R2 including the instruction fetch phase? (Assume single bus architecture)

Fundamental Concepts of BPU

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Fundamental Concepts

ALU control lines

Carry -in XOR Z TEMP

Input and output gating for one register bit.

Performing an Arithmetic or Logic Operation

R1out, Yin R2out, SelectY, Add, Zin Zout, R3in

Memory -b us data lines

Internal processor bus

Fetching a Word from Memory

Address into MAR; issue Read operation; data into MDR.

Connection and control signals for register MDR.

Fetching a Word from Memory

Execution of a Complete Instruction

Execution of a Complete Instruction

R3out , MAR in , Read R1out , Y in , WMF C

MDR out , SelectY,Add, Zin Zout , R1 in , End

ALU control lines

Figure 7.1. Single-bus organization of the datapath inside a processor.

Execution of a Complete Instruction

R3out , MAR in , Read R1out , Y in , WMF C

MDR out , SelectY,Add, Zin Zout , R1 in , End

ALU control lines

Figure 7.1. Single-bus organization of the datapath inside a processor.

Execution of Branch Instructions

Execution of Branch Instructions

Control sequence for an unconditional branch instruction.

Figure 7.8. T hree-b us or ganization of the datapath.

ALU simply passes one of ts two input operands unmodified to bus C

Add R4, R5, R6

ALU control lines

Carry -in XOR Z TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

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