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ECE645 Lecture6 Multiadd

The document summarizes multioperand addition techniques. It describes implementing the addition of multiple operands using a tree of carry-save adders (CSAs) to reduce the operands down to two, which are then added using a carry-propagate adder (CPA). It discusses tradeoffs between Wallace and Dadda trees and provides examples of CSA trees for adding various numbers of operands. It also introduces parallel counters as an alternative to CSA trees for performing multioperand addition.

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Yermakov Vadim Ivanovich
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29 views

ECE645 Lecture6 Multiadd

The document summarizes multioperand addition techniques. It describes implementing the addition of multiple operands using a tree of carry-save adders (CSAs) to reduce the operands down to two, which are then added using a carry-propagate adder (CPA). It discusses tradeoffs between Wallace and Dadda trees and provides examples of CSA trees for adding various numbers of operands. It also introduces parallel counters as an alternative to CSA trees for performing multioperand addition.

Uploaded by

Yermakov Vadim Ivanovich
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Lecture 6

Multioperand Addition

Required Reading
Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design

Chapter 8, Multioperand Addition


Note errata at:
http://www.ece.ucsb.edu/~parhami/text_comp_arit_1ed.htm#errors

Recommended Reading
J-P. Deschamps, G. Bioul, G. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems Chapter 11.1.12 Multioperand Adders

Applications of multioperand addition

Multiplication p=ax s=

Inner product

x(i) y(i) = p(i)


i=0
i=0

n-1

n-1

Number of bits of the result

S=

x(i)
i=0

n-1

x(i) [0..2k-1]

Smin = 0

Smax = n (2k-1) =

# of bits of S = log2 (Smax + 1) = log2 (n (2k-1) + 1) = k + log2 n

log2 n 2k =

Serial implementation of multioperand addition

Adding 7 numbers in the binary tree of adders

Ripple-carry adders at levels i and i+1

Example: Adding 8 3-bit numbers

Ripple-Carry Carry Propagate Adder (CPA)

an-1 bn-1 cn FA cn-1 ... c3

a2 b2 FA

a1 b1 c2
FA

a0 b0 c1
FA c0

sn-1

s2

s1

s0

Carry Save Adder (CSA)

an-1 bn-1 cn-1


FA ...

a2 b2 c2
FA

a1 b1 c1
FA

a0 b0 c0
FA

cn

sn-1 cn-1

s3 c3

s2 c2

s1 c1

s0

A Ripple-Carry vs. Carry-Save Adder

Operation of a Carry Save Adder (CSA)

Example
24 23 22 21 20

x y z

0 1 0 1 0 1 1 0 1 1 1 0 1 1 1

0 0 1 1 0 s c 1 1 0 1 1

x+y+z = s + c

Carry propagate and carry-save adders in dot notation

Specifying full- and half-adder blocks in dot notation

Carry-save adder for four operands


x3 x2 x1 x 0 y3 y2 y1 y 0 z3 z2 z1 z 0 w3 w2 w1 w0
s3 s2 s1 s 0 c4 c3 c2 c1 w3 w2 w1 w0 c4 s 3 s 2 s 1 s 0 c4 c 3 c 2 c 1 S5 S4 S3 S2 S1 S0

Carry-save adder for four operands

c4

s3

c3

s2

c2

s1

c1

s0

c4

s3

c3

s2

c2

s1

c1

s 0

Carry-save adder for four operands


x
4

y
4
4

z
4

CSA
c s

CSA
c CPA S

Carry-save adder for six operands

CSA tree

Implementation of one-bit slice

Tree of carry save adders reducing seven numbers to two

Addition of seven six-bit numbers in dot notation

Adding seven k-bit numbers: block diagram

Relationship Between Number of Inputs and Tree Height

Parameters of tree carry-save adders (1) Latency


LatencyCSA = h(n) TFA + LatencyCPA(k, n)

Tree height for n operands Component Adders CSA CPA Widths k .. k + log2 n k + log2 n typically close to k bits

Parameters of tree carry-save adders (2)


Maximum number of inputs that can be reduced to two by an h-level tree, n(h) n(0) = 2 3 n(h) = n(h-1) 2

n(1) = 3 n(2) = 4 n(3) = 6

n(4) = 9 n(5) = 13 n(6) = 19

( )

3 h-1 < n(h) 2 2

( )

3 h 2

Parameters of tree carry-save adders (3)


Smallest height of the tree carry save adder for n operands, h(n)

h(n) = 1 + h h(2) = 0

2 n 3

h(n) log 3
2

( )

n 2

Wallace vs. Dadda Trees (1)


Wallace trees Reduce the size of the final Carry Propagate Adder (CPA) Optimum from the point of view of speed Dadda trees Reduce the cost of the carry save tree Optimum (among the CSA trees) from the point of view of area

Wallace vs. Dadda Trees (2)


Wallace reduces number of operands at earliest opportunity Goal of this is to have smallest number of bits for CPA adder However, sometimes having a few bits longer CPA adder does not affect the propagation delay significantly (i.e. carry-lookahead) Dadda seeks to reduce the number of FA and HA units May be at the cost of a slightly larger final CPA

Wallace Tree

Dadda Tree

5-to-3 Parallel Counter


24 23 22 21 20

a b c d e

0 1 1 1 1

1 1 0 0 1

0 0 1 1 1

1 1 1 1 1

0 1 1 1 1

0 1 1 1 0 s0 0 1 1 0 0 s1 s2 1 0 0 1 1

a+b+c+d+e = s0+s1+s2

Implementation of 1-bit of 5-to-3 parallel counter using single CLB slice of a Virtex FPGA
S2

d c b a

LUT G 0

S1

d c b a

LUT F

S0

Carry Save Adder vs. 5-to-3 Parallel Counter


a w w b w c d e w w a b c d e

CSA
s2

PC
s1 s0

CSA

CSA CPA
w

CSA
CPA
w y=a+b+c+d+e mod 2w

y=a+b+c+d+e mod 2w

Generalized Parallel Counters


Multicolumn reduction

(5, 5; 4)-counter Unequal columns

Fig. 8.17 Dot notation for a (5, 5; 4)-counter and the use of such counters for reducing five numbers to two numbers.

Generalized parallel counter = Parallel compressor (2, 3; 3)-counter

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