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Memory Interfacing

Memory Interfacing with 8051

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150 views

Memory Interfacing

Memory Interfacing with 8051

Uploaded by

abhi198808
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Chapter 14 8051 interfacing to external memory

Semiconductor Memory

Memory capacity The number of bits that a semiconductor memory chip can store is called chip capacity.

It can be in units of Kbits (kilobits), Mbits (megabits), and so on.

Semiconductor Memory

Memory organization Memory chips are organized into number of locations within the IC. a

Each location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is designed internally.
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Speed
The speed of the memory chip is commonly referred to as its access time. The access time of memory chips varies from a few nanoseconds to hundreds of nanoseconds, depending on the IC technology used in the design and a fabrication process.

ROM (read-only memory) ROM is a type of memory that does not lose its contents when the power is turned off. For this reason, ROM is also called nonvolatile memory.

PROM (programmable ROM) and OTP PROM is programmed by blowing the fuses. If the information burned into PROM is wrong, that PROM must be discarded since its internal fuses are blown permanently.

EPROM (erasable programmable ROM) and UVEPROM )


EEPROM (Electrically Erasable Programmable read only Memory)

Flash memory EPROM

flash memory can be programmed while it is in its socket on the system board.

flash memory is semiconductor memory with access time in the range of 100 ns compared with disk access time in the range of tens of milliseconds.

Mask ROM

Mask ROM refers to a kind of ROM in which the contents


are programmed by the IC manufacturer.

Mask ROM is used when the needed volume is high

(hundreds or thousands) and it is absolutely certain that the contents will not change.
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RAM (random access memory)


RAM memory is called volatile memory since cutting off the power to the IC results in the loss of data.

SRAM (static RAM)


Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in order to keep their data. This is in contrast to DRAM.

DRAM (dynamic RAM)


uses a capacitor to store each bit requires constant refreshing due to leakage
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NV-RAM (nonvolatile RAM)


New type of nonvolatile RAM called NV-RAM. Like other RAMS, it allows the CPU to read and write to it, but when the power is turned off the contents are not lost.

Figure 143 Figure 142 2Kx8 SRAM Pins

256Kx1 DRAM

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Memory Address Decoding

Simple logic gate address decoder

Figure 144

Logic Gate as Decoder


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Memory Address Decoding

Using the 74LS138 3-8 decoder

Figure 145 74LS138 Decoder (Reprinted by permission of Texas Instruments, Copyright Texas Instruments, 1988)
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Memory Address Decoding

Figure 146

74LS138 as Decoder

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Using programmable logic as an address decoder The advantage of these chips is that they can be programmed for any combination of address ranges, and so are much more versatile.

PALs and GALS have 10 or more inputs (in


contrast to 6 in the 74138) means that they can accommodate more address inputs.

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8031/51 Interfacing With External Rom


EA pin Connect the EA pin to Vcc to indicate that the program code is stored in the mC's on-chip ROM. To indicate that the program code is stored in external ROM, this pin must be connected to GND.

Figure 147

8051 Pin Diagram


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8031/51 INTERFACING WITH EXTERNAL ROM

Figure 148 74LS373 D Latch

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8031/51 Interfacing With External Rom

P0 and P2 role in providing addresses

Figure 149

Address/Data Multiplexing

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8031/51 INTERFACING WITH EXTERNAL ROM

Figure 1410

Data, Address, and Control Buses for the 8031


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8031/51 INTERFACING WITH EXTERNAL ROM

Figure 1411

8031 Connection to External Program ROM

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8031/51 INTERFACING WITH EXTERNAL ROM

PSEN

Figure 1412

On-chip and Off-chip Program Code Access

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8031/51 INTERFACING WITH EXTERNAL ROM On-chip and off-chip code ROM

In such a system we still have EA = Vcc,


meaning that upon reset the 8051 executes the on-chip program first; then, when it reaches the

end of the on-chip ROM it switches to external


ROM for the rest of the program code.

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8051 Data Memory Space

Data memory space

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Figure 1413

8051 Connection to External Data ROM

8051 Data Memory Space

External ROM for data

For the ROM containing the program code, PSEN


is used to fetch the code.

For the ROM containing data, the RD signal is used to fetch the data.

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8051 Data Memory Space

MOVX instruction

Figure 1414 8031 Connection to External Data ROM and External Program ROM

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8051 Data Memory Space

MOVX instruction for external RAM data

Figure 1415

8051 Connection to External Data RAM

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Write a Program to transfer an array of 10 bytes stored in location starting from 8000H in this RAM to location starting at 9000H.
Data1 Data2 Count EQU EQU EQU 8000H 9000H 10 MOVX @DPTR,A INC DPTR MOV R0,DPL MOV R1,DPH POP DPL POP DPH DJNZ R2,START END

START:

ORG 0000H MOV R2,#Count MOV DPTR,#Data2 MOV R0,DPL MOV R1,DPH MOV DPTR,#Data1 MOVX A,@DPTR INC DPTR PUSH DPH PUSH DPL MOV DPH,R1 MOV DPL,R0

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8051 Data Memory Space

A single external ROM for code and data

Figure 1416

A Single ROM for Both Program and Data

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8031 system with ROM and RAM

Figure 1417 8031 Connection to External Program ROM, Data RAM, and Data ROM

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Interfacing to large external memory

Figure 1418

8051 Accessing 256Kx8 External NV-RAM

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