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Mu0 Core

This document discusses the design of a simple CPU core called MU0 for educational purposes. It begins by outlining the MU0 instruction set, which includes instructions for load, store, arithmetic, and conditional jump operations. It then describes the design of the MU0 datapath and control logic. The datapath includes components like a program counter, instruction register, accumulator, and arithmetic logic unit. The control logic synchronizes the datapath and determines the signals to execute each instruction type over multiple clock cycles. Signal timings and operations are defined for each instruction code. The goal is to design, verify and prototype the MU0 processor in VHDL for implementation on an FPGA as a learning project.

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Gihoon Jung
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369 views22 pages

Mu0 Core

This document discusses the design of a simple CPU core called MU0 for educational purposes. It begins by outlining the MU0 instruction set, which includes instructions for load, store, arithmetic, and conditional jump operations. It then describes the design of the MU0 datapath and control logic. The datapath includes components like a program counter, instruction register, accumulator, and arithmetic logic unit. The control logic synchronizes the datapath and determines the signals to execute each instruction type over multiple clock cycles. Signal timings and operations are defined for each instruction code. The goal is to design, verify and prototype the MU0 processor in VHDL for implementation on an FPGA as a learning project.

Uploaded by

Gihoon Jung
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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CPE 626 Advanced VLSI Design Lecture 2

Aleksandar Milenkovic
http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04F/ [email protected]

Assistant Professor Electrical and Computer Engineering Dept. University of Alabama in Huntsville

LaCASA IP Library

Advanced VLSI Design

The Need for IP Cores


Benefits of HDL-based design
Portability Technology independence Design cycle reduction Automatic synthesis and Logic optimization

But, the gap between available chip complexity and design productivity continues to increase

Chip Complexity 58% / year

Design productivity 21% / year

Use IP cores
A. Milenkovic 2

LaCASA IP Library

Advanced VLSI Design

New Generation of Designers


Emphasis on hierarchical IP core design Design systems, not components! Understand hardware/software co-design Understand and explore design tradeoffs between complexity, performance, and power consumption Design a soft processor/micro-controller core

A. Milenkovic

LaCASA IP Library

Advanced VLSI Design

UAH Library of Soft Cores


Microchips PIC18 micro-controller Microchips PIC16 micro-controller Intels 8051 ARM Integer CPU core FP10 Floating-point Unit (ARM) Advanced Encryption Standard (AES) Video Processing System on a Chip

A. Milenkovic

LaCASA IP Library

Advanced VLSI Design

Design Flow for CPU Cores


Reference Manual

Instruction Set Analysis Dpth&Cntr Design ASM Test Programs C Programs

VHDL Model

MPLAB IDE

C Compiler

Verification

iHex2Rom

Synthesis& Implementation
A. Milenkovic 5

LaCASA IP Library

Advanced VLSI Design

Soft IP Engineering Cycle


Encompasses all relevant steps
Design Improvements Specification

Design Measurements (Compl.&Perf.&Power) FPGA Implementation Modeling Simulation & Verification

Put together knowledge in digital design, HDLs, computer architecture, programming languages State-of-the-art devices Work in teams

A. Milenkovic

LaCASA IP Library

Advanced VLSI Design

PIC18 Greetings

http://www.ece.uah.edu/~milenka/pic18/pic.html

A. Milenkovic

Advanced VLSI Design

Designing a simple CPU in 60 minutes


LaCASA step-by-step tutorial
http://www.ece.uah.edu/~lacasa/tutorials/mu0/mu0tutorial.html

Design, verify, implement, and prototype a rudimentary processor MU0 Modeling using VHDL Simulation using ModelSim Implement using Xilinx ISE and a SpartanII device

A. Milenkovic

Advanced VLSI Design

MU0 A Simple Processor


Instruction format Instruction set
Instruction LDA S STO S ADD S SUB S JMP S JGE S JNE S STP Opcode 0000 0001 0010 0011 0100 0101 0110 0111 Effect ACC := mem16[S] mem16[S] := ACC ACC := ACC + mem16[S] ACC := ACC - mem16[S] PC := S if ACC >= 0 PC := S if ACC !=0 PC := S stop

4 bits opcode

12 bits S

A. Milenkovic

Advanced VLSI Design

MU0 Datapath Example


Program Counter PC Accumulator - ACC Arithmetic-Logic Unit ALU Instruction Register Instruction Decode and Control Logic
ad dress bus

Follow the principle that the memory will be limiting factor in design: each instruction takes exactly the number of clock cycles defined by the number of memory accesses it must take.

PC

co ntro l

IR memo ry

AL U

ACC

da ta b us
A. Milenkovic 10

Advanced VLSI Design

MU0 Datapath Design


Assume that each instruction starts when it has arrived in the IR Step 1: EX (execute)
LDA S: ACC <- Mem[S] STO S: Mem[S] <- ACC ADD S: ACC <- ACC + Mem[S] SUB S: ACC <- ACC Mem[S] JMP S: PC <- S JGE S: if (ACC >= 0) PC <- S JNE S: if (ACC != 0) PC <- S

Step 2: IF (fetch the next instruction)


Either PC or the address in the IR is issued to fetch the next instruction address is incremented in the ALU and value saved into the PC

Initialization
Reset input to start executing instructions from a known address; here it is 000hex
provide zero at the ALU output and then load it into the PC register
11

A. Milenkovic

Advanced VLSI Design

MU0 RTL Organization


Control Logic
Asel Bsel ACCce (ACC change enable) PCce (PC change enable) IRce (IR change enable) ACCoe (ACC output enable) ALUfs (ALU function select) MEMrq (memory request) RnW (read/write) Ex/ft (execute/fetch)

A. Milenkovic

12

Advanced VLSI Design

MU0 control logic In p ut s


Op c o de Ex / f t ACC1 5 In s t ruc t i o n Re s e t ACCz Reset xxxx 1 x x x LDA S 0000 0 0 x x 0000 0 1 x x STO S 0001 0 0 x x 0001 0 1 x x ADD S 0010 0 0 x x 0010 0 1 x x SUB S 0011 0 0 x x 0011 0 1 x x JMP S 0100 0 x x x JGE S 0101 0 x x 0 0101 0 x x 1 JNE S 0110 0 x 0 x 0110 0 x 1 x STOP 0111 0 x x x

Out p ut s Bs el PCc e ACCo e MEMrq Ex / f t As e l ACCc e IRc e ALUf s Rn W 0 0 1 1 1 0 =0 1 1 0 1 1 1 0 0 0 =B 1 1 1 0 0 0 1 1 0 B+1 1 1 0 1 x 0 0 0 1 x 1 0 1 0 0 0 1 1 0 B+1 1 1 0 1 1 1 0 0 0 A+B 1 1 1 0 0 0 1 1 0 B+1 1 1 0 1 1 1 0 0 0 A-B 1 1 1 0 0 0 1 1 0 B+1 1 1 0 1 0 0 1 1 0 B+1 1 1 0 1 0 0 1 1 0 B+1 1 1 0 0 0 0 1 1 0 B+1 1 1 0 1 0 0 1 1 0 B+1 1 1 0 0 0 0 1 1 0 B+1 1 1 0 1 x 0 0 0 0 x 0 1 0

A. Milenkovic

13

Advanced VLSI Design

LDA S (0000)
Ex/ft = 1

Ex/ft = 0

B+1

A. Milenkovic

14

Advanced VLSI Design

STO S (0001)
Ex/ft = 1 Ex/ft = 0

B+1

A. Milenkovic

15

Advanced VLSI Design

ADD S (0010)
Ex/ft = 1 Ex/ft = 0

A+B

B+1

A. Milenkovic

16

Advanced VLSI Design

SUB S (0011)
Ex/ft = 1 Ex/ft = 0

A-B

B+1

A. Milenkovic

17

Advanced VLSI Design

JMP S (0100)

Ex/ft = 0

B+1

A. Milenkovic

18

Advanced VLSI Design

JGE S (0101)
Ex/ft = 0, ACC15 = 0

Ex/ft = 0, ACC15 = 1

B+1

B+1

A. Milenkovic

19

Advanced VLSI Design

JNE S (0110)
Ex/ft = 0, ACCz = 0

Ex/ft = 0, ACCz = 1

B+1

B+1

A. Milenkovic

20

Advanced VLSI Design

STP (001)

Ex/ft = 0

A. Milenkovic

21

Advanced VLSI Design

Reset

Ex/ft = 0

A. Milenkovic

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