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Lecture 1 - Multiplexer, ROM, PLA and PAL

The document discusses digital system design topics including a 16 to 1 multiplexer, 4-variable function using multiplexers, a 3-bit BCD to Gray code converter, generating binary waveforms using ROM, a 7-segment display using ROM, a binary to ASCII converter using ROM, designing combinational circuits using PLA, implementing a 3-bit BCD to Gray code converter using PLA, and a full adder implementation using PAL.

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222 views47 pages

Lecture 1 - Multiplexer, ROM, PLA and PAL

The document discusses digital system design topics including a 16 to 1 multiplexer, 4-variable function using multiplexers, a 3-bit BCD to Gray code converter, generating binary waveforms using ROM, a 7-segment display using ROM, a binary to ASCII converter using ROM, designing combinational circuits using PLA, implementing a 3-bit BCD to Gray code converter using PLA, and a full adder implementation using PAL.

Uploaded by

shavali56
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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DIGITAL SYSTEM DESIGN

SATISH KASHYAP. B

www.satishkashyap.com

Design : Quad Multiplexer with Bus inputs and outputs

A 16 to 1 Multiplexer Implementation

4 - variable function using 8:1 MUX

4 - variable function using 4:1 MUX

4 - variable function using 2:1 MUX

Design a 3 bit BCD to Gray code converter BCD x1 x2 x3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 GRAY z2 0 0 1 1 1 1 0 0

z1 0 0 0 0 1 1 1 1

z3 0 1 1 0 0 1 1 0

Design a 3 bit BCD to Gray code converter

Generate a sequence of four binary waveforms using ROM

Design a 7 Segment Display using ROM

Design a Binary to ASCII code converter using ROM

Designing Multiple Output Combinational Circuit using PLA

Design the following using PLA

Design 3 bit BCD to Gray code converter using PLA


BCD x1 0 0 0 0 1 1 1 1 x2 0 0 1 1 0 0 1 1 x3 0 1 0 1 0 1 0 1 z1 0 0 0 0 1 1 1 1 GRAY z2 0 0 1 1 1 1 0 0 z3 0 1 1 0 0 1 1 0

Practical Design

Full Adder implementation using PAL

Part of Logic Diagram for 16R4 PAL

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