GNU RADIO INTRODUCTION

BY SUMIT ABHICHANDANI VEERA BAPINEEDU NUNE TUSHAR AMBRE KIRAN KUMBHAR SATHYA SRIDHARAN UKASH

OUTLINE

Introduction USRP USRP 2 USRP vs USRP2 References

INTRODUCTION

SOFTWARE RADIO
WHAT IS GNU RADIO

SOFTWARE RADIO
An implementation technology A technique for moving digital signal processing as close as

possible to the antenna Replacing rigid Hardware with flexible software based solutions
A software (defined) radio is a radio that includes a

transmitter in which the operating parameters of the transmitter, including the frequency range, modulation type or maximum radiated or conducted output power can be altered by making a change in software without making any hardware changes.

Defining software radio using tiers...

The SDR Forum has defined the following tiers, describing evolving capabilities in terms of flexibility

Tier 0
The Hardware Radio:
Hardware components only cannot be modified ( Need physical intervention)

Defining software radio using tiers...

The SDR Forum has defined the following tiers, describing evolving capabilities in terms of flexibility
Tier 0:The Hardware Radio Tier 1
Software Controlled Radio (SCR):
Only control functions software Extends to inter-connects, power levels etc. but not

to frequency bands and/or modulation types

Defining software radio using tiers...

The SDR Forum has defined the following tiers, describing evolving capabilities in terms of flexibility
Tier 0: The Hardware Radio Tier 1: Software Controlled Radio (SCR) Tier 2

Software Defined Radio (SDR): provide software control of provide control of a variety of modulation techniques, such as Wide-band or narrow-band operation, Communications security functions (such as hopping), Waveform requirements of current and evolving standards over a broad frequency range. The frequency bands covered may still be constrained at the front-end requiring a switch in the antenna system

Defining software radio using tiers...

The SDR Forum has defined the following tiers, describing evolving capabilities in terms of flexibility
Tier 0: The Hardware Radio Tier 1: Software Controlled Radio (SCR)

Tier 2: Software Defined Radio (SDR)

Tier 3 Ideal Software Radio (ISR): Even the analog amplification or heterodyne mixing prior to digitalanalog conversion is eliminated. Programmability extends to the entire system with analog conversion only at the antenna, speaker and microphones.

Defining software radio using tiers...

The SDR Forum has defined the following tiers, describing evolving capabilities in terms of flexibility
Tier 0: The Hardware Radio Tier 1: Software Controlled Radio (SCR) Tier 2: Software Defined Radio (SDR) Tier 3:Ideal Software Radio (ISR) Tier 4 (for comparison purpose only)

Ultimate Software Radio (USR): Accepts fully programmable traffic supports a broad range of frequencies, air-interfaces & applications software. can switch from one air interface format to another in milliseconds, use GPS to track the users location, store money using smartcard technology, or provide video so that the user can watch a local broadcast station or receive a satellite transmission.

Defining software radio using tiers...

The SDR Forum has defined the following tiers, describing evolving capabilities in terms of flexibility
Tier 0: The Hardware Radio Tier 1: Software Controlled Radio (SCR)

Tier 2: Software Defined Radio (SDR)

Tier 3: Ideal Software Radio (ISR) Tier 4 : Ultimate Software Radio (USR) Cognitive radio (CR) : wireless communication in which a transceiver can intelligently detect which communication channels are in use and which are not, and instantly move into vacant channels while avoiding occupied ones.

GNU RADIO

BLOCK DIAGRAM
TRANSMIT PATH
RECEIVE RF FRONT END ADC YOUR CODE HERE!

XMIT RF FRONT END

DAC

YOUR CODE HERE!

PLATFORMS
WINDOWS
Cygwin MinGW

LINUX
Ubuntu

SOFTWARE
GNU Radio provides a library of signal processing

blocks and the glue to tie it all together. LANGUAGES

o o o

C++ PYTHON SWIG

APPLICATION
A TiVo equivalent for radio, capable of recording multiple stations simultaneously. Time Division Multiple Access (TDMA) waveforms. A passive radar system that takes advantage of broadcast TV for its signal source.

For those of you with old TVs hooked to antennas, think about the flutter you see when airplanes fly over. Radio astronomy. TETRA transceiver. Digital Radio Mundial (DRM). Software GPS. Distributed sensor networks. Distributed measurement of spectrum utilization. Amateur radio transceivers. Ad hoc mesh networks. RFID detector/reader. Multiple input multiple output (MIMO) processing.

Overall Architecture

Hardware

Basic USRP facts 4*ADC, 12 bit @ 64MSPS

4*DAC, 14 bit @ 128MSPS

Altera EP1C12 FPGA for preprocessing tasks

USB 2.0 interface to host PC (32 MB/s)

Universal Software Radio Peripheral

Mother Board

Four digital downconverters with programmable decimation rates Two digital upconverters with programmable interpolation rates Capable of processing signals up to 16 MHz wide Modular architecture supports wide variety of RF daughterboards Auxiliary analog and digital I/O support complex radio controls such as RSSI and AGC Fully coherent multi-channel systems (MIMO capable)

Transceiver port

ADC

Altera FPGA

Power

USB 2.0

ARCHITECTURE

ARCHITECTURE
Sender
User-defined Code USB USRP (mother board) RF Front end

FPGA

DAC

PC
One mother board support up to four daughter boards. Several kinds of daughter boards available

modules that has been provided in GNU radio project to communicate between two end systems

Transmitter/Reciever
23

Sender
User-defined Code USB FPGA DAC RF Front end

PC

USRP (mother board)

Receiver
User-defined Code USB FPGA ADC RF Front end

ARCHITECTURE
Sender
User-defined Code USB USRP (mother board) RF Front end

FPGA

DAC

PC
Support USB2.0/At this stage, USB 1.x is not supported at all 1. 2. Support 32MB/sec across the USB. Samples are in 16-bit signed integers in IQ format, 16-bit I and 16-bit Q data (complex), resulting in 8M complex samples/sec across the USB.

ARCHITECTURE
Sender
User-defined Code USB USRP (mother board) RF Front end

FPGA

DAC

PC
Includes digital down converters (DDC) implemented with cascaded integrator-comb (CIC) filters (for receivers). Digital up converters (DUCs) on the transmit side are actually contained in the AD9862 CODEC chips, not in the FPGA. The only transmit signal processing blocks in the FPGA are the interpolators.

FPGA

Multiplexer
MUX is like router Decides which ADC to

each DDC

DDC

Down converts the IF

band into base band

Decimates the signal

to data rate so it can be transferred to usb.

ARCHITECTURE
Sender
User-defined Code USB USRP (mother board) RF Front end

FPGA

DAC

PC
4 high-speed 14-bit DA converters, DAC clock frequency is 128 MS/s (stay below about 50MHz or so to make filtering easier.) 4 high-speed 12-bit AD converters, sampling rate is 64M samples per second.

Further developments in Gnu radio

The current GNU Radio architecture primarily aimed at

Streaming Radio The current scheduler relies on a steady stream of input data to processing blocks Packet Radio (TDD/TDMA) is therefore difficult to implement with precise timing Architectural change is implemented (USRP 2) Processing of arbitrarily sized blocks of data Treats input as messages, Data, Metadata Include modification to FPGA Python replaced by C++ as programming language

USRP2

FEATURES
100 MS/s 14-bit dual (IQ) ADCs 400 MS/s 16-bit dual (IQ) DACs

Gigabit Ethernet interface

Allows for 25 MHz of RF BW each way @16bits Wide enough for WiFi!

Bigger FPGA w/Multipliers (Spartan 3)

1 MB high-speed on-board SRAM High speed serial expansion interface

Features continued:
Can operate without host computer External Frequency Reference Input

Flexible choice of reference, not just 10 MHz

Pulse per second (PPS) input for precise Timing Uses the same daughterboards as USRP1

- Only holds 1 TX and 1 RX - MIMO via expansion interface

USRP2 FPGA
Spartan 3

- ~40K logic cells, Lots of RAM and multipliers

32-bit RISC Processor soft core - 50 MHz

- GCC tool chain

FIFOs and full crossbar between interfaces Precise timing control (10ns) for TDMA, etc.

FPGA can handle High sample rate processing, like digital up- and down conversion. Lower sample rate operations can be done in the FPGA, which contains a 32-bit RISC microprocessor. The larger FPGA allows the USRP2 to be used as a standalone system without a host computer in many cases

DAUGHTER BOARDS
Provide transformation of mother board into a

complete RF transreceiver system .

Daughter boards provide various features which

helps their integration into complex systems.

FEATURES:
30 MHz transmit and receive bandwidth

Fully synchronous design, MIMO capable

All functions controllable from software or FPGA Independent local oscillators (LOs) for TX and RX

enable split-frequency operation &built-in T/R switching TX and RX on same connector or use auxiliary RX port 16 digital I/O lines to control external devices

VARIOUS DAUGHTER BOARDS USED

WBX0510 Frequency Range: 50 MHz to 1 GHz Transmit Power: 100mW (20dBm) RFX900 Frequency Range: 750 to 1050 MHz Transmit Power: 200mW (23dBm) RFX1200 Frequency Range: 1150 to 1450 MHz Transmit Power: 200mW (23dBm) RFX1800 Frequency Range: 1.5 to 2.1 GHz Transmit Power: 100mW (20dBm) RFX2400 Frequency Range: 2.3 to 2.9 GHz Transmit Power: 50mW (17dBm) XCVR2450 Frequency Range: 2.4 to 2.5 GHz, and 4.9 to 5.9 GHz Transmit Power: 100mW (20dBm)

RFX900
Frequency Range: 750 to 1050 MHz Transmit Power: 200mW (23dBm) The RFX900 comes with a 902928 MHz ISM-band filter installed for filtering strong out-ofband signals (like pagers). The filter can easily be bypassed to allow usage over the full frequency range, enabling use with cellular, Paging and two-way radio, in addition to the ISM band.

New Transceiver Daughterboards (coming in '09)

50 MHz to 1 GHz Transceiver

800 MHz to 2.2 GHz Transceiver

Both are MIMO Capable, 100+ mW output

 Extensive use of Opencores.org

Processor
Wishbone Crossbar switch

Wishbone Bus

USRP2 uses cross bar switches to perform MIMO via expansion interface

PROPERTIES/COMPONENTS
REFERENCE CLOCK:

External Input of 10 MHz (sine or square) can be provided. (DC blocked terminated at 50 ohms). Stability of the clock is 20ppm. Internal Input of 100 MHz (time stamped) is used by USRP2. PPS: Signals (0-5V) go directly to FPGA hence faster sync pulse is possible. PPS is for precise timing. (not DC blocked but AC terminated at 50 ohms and DC terminated at 1Kohms.

Properties/components Contd.
RF Bandwidth: 25 MHz at 16 bits.

Chipset: National Semiconductor PHY chip,

DP83856. SD Card: Supposedly supports stand-alone mode as delay can be reduced in it. MIMO: USRP2 has MIMO cable port to exchange clock and data among USRP2 boards.

Properties/components Contd.
AeMB processor: Heart of USRP2.

It performs : Configuration of FPGA. Reports FPGA about all the peripherals. Controls Channel for daughterboard operation.
It is clocked at 50 MHz.

Properties/components Contd.
1 MB SRAM:

Used as: Large buffer to hold premodulated packets. Large FIFO to hold bursts of samples at higher rates than Ethernet. Auxiliary RAM for either Data or Instructions or both.

Properties/components Contd.
High Speed Serial Link:

Four differential signals in each direction:

Carries data at 2 Gbps each way. Reference clock for phase locking oscillators. Time sync signal. One high speed differential link available for user.

Network of USRP2 Line Cards:

Two USRP2s linked directly. Four or more USRP2s linked by hub using MIMO.

APPLICATION
FM RADIO

RF ID READER
CELLULAR GSM BASE STATION GPS RECIVER

DIGITAL TV DECODER
AMATUER RADIO

USRP v/S USRP 2

USRP INTERFACE FPGA ADC SAMPLES USB2.0 ALTERA EP1C12 12- bit 64 MS/S USRP2 GIGABIT ETHERNET Xilinx Spartan 3 2000 14- bit, 100 MS/S

DAC SAMPLES
DAUGHTER BOARD SRAM

14 bit, 128 MS/s

2 TX, 2 RX NONE

16- bit, 400 MS/S

1 TX, 1 RX 1 MEGABYTE

USB 2.0 and Ethernet

USB 2.0 Speed Mbps Ethernet Gbps

Driver Switch

Required Not required

Not Required Required (Gigabit Switch)

ADC and DAC

Increase in bits

Increased Resolution SNR= 6.02 N + 10.8 - 20log(X p/x) (6 db increase per bit)
Sampling rate

Increased Bandwidth

USRP can digitize a band as wide as 32 MHz

USRP2 can digitize bandwidth as wide as 64 MHz

DAUGHTERBOARD

Can USRP2 support 2 TX or 2 RX Simultaneously?

NO USRP2 supports 1 RX and 1 TX daughterboard OR 1 Transceiver Daughter Board

2 RX or two TX can be connected at a time using

MIMO cable.

References
GNU Radio-An introduction, Jesper M. Kristensen

Department of Electronic Systems Technology Platforms Section [email protected] ,Mobile Developer Days 2007. GNU Radio & USRP, presentationWireless Center,

Copenhagen University College of Engineering Center for Software Defined Radio, Aalborg University. http://gnuradio.org/trac/wiki http://www.snowymtn.ca/gnuradio Ettus Research LLC - http://ettus.com - [email protected] GNU Radio Home Page - Wiki, Source Code, Schematics, Mailing Lists - http://gnuradio.org/trac

THE END