VHDL Examples Combinational Logic

A 2-to-1 multiplexer WITH-SELECT-WHEN statement

s w0 w1
0 1

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s f END mux2to1 ;

: IN : OUT

STD_LOGIC ; STD_LOGIC ) ;

(a) Graphical symbol

ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f <= w0 WHEN '0', w1 WHEN OTHERS ; END Behavior ;

s 0 1

f
w0 w1

(b) Truth table

Figure 6.27

VHDL code for a 2-to-1 multiplexer

A 2-to-1 multiplexer WHEN-ELSE statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ;

s w0 w1
0 1

(a) Graphical symbol

f
w0 w1

ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ;
Figure 6.31

0 1

(b) Truth table

A 2-to-1 multiplexer using a conditional signal assignment

A 2-to-1 multiplexer IF statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ;
s

ENTITY mux2to1 IS PORT ( w0, w1, s f END mux2to1 ;

: IN : OUT

STD_LOGIC ; STD_LOGIC ) ;

w0 w1

0 1

(a) Graphical symbol

ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN f <= w0 ; IF s = '1' THEN f <= w1 ; END IF ; END PROCESS ; END Behavior ;
Figure 6.39

s 0 1

f
w0 w1

(b) Truth table

Alternative code for a 2-to-1 multiplexer

A 2-to-1 multiplexer CASE statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s f END mux2to1 ;
s

: IN STD_LOGIC ; : OUT STD_LOGIC ) ;

w0 w1

0 1

ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN CASE s IS WHEN '0' => f <= w0 ; WHEN OTHERS => f <= w1 ; END CASE ; END PROCESS ; END Behavior ;
Figure 6.45

(a) Graphical symbol

s 0 1

f
w0 w1

(b) Truth table

A CASE statement that represents a 2-to-1 multiplexer

A 4-to-1 multiplexer
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 s f END mux4to1 ;

s0 s1 w0 w1 w2 w3
00 01

s1 s0 0 0 1 1 0 1 0 1

f w0 w1 w2 w3

10 11

(a) Graphic symbol

(b) Truth table

: IN : IN : OUT

STD_LOGIC ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;
Figure 6.28

VHDL code for a 4-to-1 multiplexer

A 4-to-1 multiplexer
s0 w0 s1 w1 f w2

w3

LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE mux4to1_package IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 s f END COMPONENT ; END mux4to1_package ;
Figure 6.28

: IN : IN : OUT

STD_LOGIC ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

Component declaration for the 4-to-1 multiplexer

A 16-to-1 multiplexer

s0 s1 w0 w3

w4 w7

s2 s3

w8
w11

w12 w15

Figure 6.4

A 16-to-1 multiplexer

A 16-to-1 multiplexer Structural model

LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.mux4to1_package.all ;

ENTITY mux16to1 IS PORT ( w : IN s : IN f : OUT END mux16to1 ;

STD_LOGIC_VECTOR(0 TO 15) ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;
Figure 6.29

Hierarchical code for a 16-to-1 multiplexer

A 16-to-1 multiplexer GENERATE Statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.mux4to1_package.all ;
ENTITY mux16to1 IS PORT ( w : IN s : IN f : OUT END mux16to1 ;

STD_LOGIC_VECTOR(0 TO 15) ; STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;
Figure 6.36

Code for a 16-to-1 multiplexer using a generate statement

A 2-to-4 binary decoder WITH-SELECT-WHEN statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN En : IN y : OUT END dec2to4 ;

STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ; En STD_LOGIC_VECTOR(0 TO 3) ) ;

1 1 1 1 0

w1 w0 0 0 1 1 x 0 1 0 1 x

y0 y1 y2 y3 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0

ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ;
Figure 6.30

(a) Truth table

w0 w1
En

y0 y1 y2 y3

(b) Graphic symbol

VHDL code for a 2-to-4 binary decoder

A 2-to-4 binary decoder CASE statement

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN En : IN y : OUT END dec2to4 ;

STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR(0 TO 3) ) ;

ARCHITECTURE Behavior OF dec2to4 IS BEGIN PROCESS ( w, En ) BEGIN IF En = '1' THEN CASE w IS WHEN "00" => WHEN "01" => WHEN "10" => WHEN OTHERS => END CASE ; ELSE y <= "0000" ; END IF ; END PROCESS ; END Behavior ;
Figure 6.46

y <= "1000" ; y <= "0100" ; y <= "0010" ; y <= "0001" ;

A 2-to-4 binary decoder

A 4-to-16 binary decoder - Circuit

w0 w1 w0 w1 y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15

En
w0 w1 w2

w3
En

w0 w1

En

y0 y1 y2 y3

En

w0 w1
En

y0 y1 y2 y3 y0 y1 y2 y3

w0 w1
En

Figure 6.18

A 4-to-16 decoder built using a decoder tree

A 4-to-16 binary decoder

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec4to16 IS PORT ( w : IN En : IN y : OUT END dec4to16 ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR(0 TO 15) ) ;

ARCHITECTURE Structure OF dec4to16 IS COMPONENT dec2to4 PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) ); G2: IF i=3 GENERATE Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ; END GENERATE ; END GENERATE ; END Structure ;
Figure 6.37

Hierarchical code for a 4-to-16 binary decoder

A priority encoder
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;

w3 w2 w1 w0 0 0 0 0 1 0 0 0 1 x 0 0 1 x x 0 1 x x x

y1 y0
d 0 0 1 1 d 0 1 0 1

z 0 1 1 1 1

Figure 6.32

VHDL code for a priority encoder

A priority encoder
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF priority IS BEGIN WITH w SELECT y <= "00" WHEN "0001", "01" WHEN "0010", "01" WHEN "0011", "10" WHEN "0100", "10" WHEN "0101", "10" WHEN "0110", "10" WHEN "0111", "11" WHEN OTHERS ; WITH w SELECT z <= '0' WHEN "0000", '1' WHEN OTHERS ; END Behavior ;
Figure 6.33

Less efficient code for a priority encoder

A priority encoder IF statement (1)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN y : OUT z : OUT END priority ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF priority IS BEGIN PROCESS ( w ) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = '1' THEN y <= "01" ; ELSE y <= "00" ; END IF ; END PROCESS ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;
Figure 6.40

A priority encoder specified using if-then-else

A priority encoder IF statement (2)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w y z END priority ;

: IN : OUT : OUT

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ;

ARCHITECTURE Behavior OF priority IS BEGIN PROCESS ( w ) BEGIN y <= "00" ; IF w(1) = '1' THEN y <= "01" ; END IF ; IF w(2) = '1' THEN y <= "10" ; END IF ; IF w(3) = '1' THEN y <= "11" ; END IF ; z <= '1' ; IF w = "0000" THEN z <= '0' ; END IF ; END PROCESS ; END Behavior ;
Figure 6.41

Alternative code for the priority encoder

A four-bit comparator
LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN AeqB, AgtB, AltB : OUT END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC ) ;

Figure 6.34

VHDL code for a four-bit comparator

A four-bit comparator using signed numbers

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY compare IS PORT ( A, B : IN AeqB, AgtB, AltB : OUT END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

SIGNED(3 DOWNTO 0) ; STD_LOGIC ) ;

Figure 6.35

A four-bit comparator using signed numbers

The 74381 ALU

Table 6.1

The functionality of the 74381 ALU

The 74381 ALU

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY alu IS PORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ; A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END alu ;

ARCHITECTURE Behavior OF alu IS BEGIN PROCESS ( s, A, B ) BEGIN CASE s IS WHEN "000" => F <= "0000" ; WHEN "001" => F <= B - A ; WHEN "010" => F <= A - B ; Figure 6.48 Code that WHEN "011" => F <= A + B ; represents the functionality WHEN "100" => F <= A XOR B ; of the 74381 ALU WHEN "101" => F <= A OR B ; WHEN "110" => F <= A AND B ; WHEN OTHERS => F <= "1111" ; END CASE ; END PROCESS ; END Behavior ;

The 74381 ALU

Figure 6.49

Timing simulation for the 74381 ALU code

A BCD-to-7-segment display code converter

w0 w1 w2 w3 a b c d e f g a

f
e g d

b
c

(a) Code converter

(b) 7-segment display

w3 w2 w1 w0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1

a 1 0 1 1 0 1 1 1 1 1

b 1 1 1 1 1 0 0 1 1 1

c 1 1 0 1 1 1 1 1 1 1

d
1 0 1 1 0 1 1 0 1 1

e 1 0 1 0 0 0 1 0 1 0

f
1 0 0 0 1 1 1 0 1 1

g 0 0 1 1 1 1 1 0 1 1

(c) Truth table Figure 6.25

A BCD-to-7-segment display code converter

A BCD-to-7-segment decoder
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY seg7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS -abcdefg WHEN "0000" => leds <= "1111110" ; WHEN "0001" => leds <= "0110000" ; WHEN "0010" => leds <= "1101101" ; WHEN "0011" => leds <= "1111001" ; WHEN "0100" => leds <= "0110011" ; WHEN "0101" => leds <= "1011011" ; WHEN "0110" => leds <= "1011111" ; WHEN "0111" => leds <= "1110000" ; WHEN "1000" => leds <= "1111111" ; WHEN "1001" => leds <= "1110011" ; WHEN OTHERS => leds <= "-------" ; END CASE ; END PROCESS ; END Behavior ;
Figure 6.47

A BCD-to-7-segment decoder

4 Bit Ripple Carry Adder

A(3) B(3) A(2) B(2) A(1) B(1) A(0) B(0) Cout C(4) A
Co S B Ci A Co S B Ci A Co S B Ci A Co S B Ci

C(3)

C(2)

C(1)

C(0)

Cin

Sum(3)

Sum(2)

Sum(1)

Sum(0)

Want to write a VHDL model for a 4 bit ripple carry adder. Logic equation for each full adder is: sum <= a xor b xor ci; co <= (a and b) or (ci and (a or b));

4 Bit Ripple Carry Model

library ieee; use ieee.std_logic_1164.all; entity adder4bit is port ( a,b: in std_logic_vector(3 downto 0); cin : in std_logic; cout: out std_logic; sum: out std_logic_vector(3 downto 0) ); end adder4bit; architecture bruteforce of adder4bit is -- temporary signals for internal carries signal c : std_logic_vector(4 downto 0); . begin process (a, b, cin, c) begin c(0) <= cin; -- full adder 0 sum(0) <= a(0) xor b(0) xor c(0); c(1) <= (a(0) and b(0)) or (c(0) and (a(0) or b(0))); -- full adder 1 sum(1) <= a(1) xor b(1) xor c(1); c(2) <= (a(1) and b(1)) or (c(1) and (a(1) or b(1))); -- full adder 2 sum(2) <= a(2) xor b(2) xor c(2); c(3) <= (a(2) and b(2)) or (c(2) and (a(2) or b(2))); -- full adder 3 sum(3) <= a(3) xor b(3) xor c(3); c(4) <= (a(3) and b(3)) or (c(3) and (a(3) or b(3))); cout <= c(4); end process; end bruteforce;

Straight forward implementation. Nothing wrong with this. However, is there an easier way?

4 Bit Ripple Carry Model using For Statement

architecture forloop of adder4bit is signal c : std_logic_vector(4 downto 0); -- temporary signals for internal carries. begin process (a, b, cin, c) begin c(0) <= cin; for i in 0 to 3 loop -- all four full adders sum(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i))); end loop; cout <= c(4); end process; end forloop;