80186

16-bit processor, similar to 8086

80186 is a highly integrated microprocessor which effectively combine up to 20 of the most common system components onto a

single chip
16-bit data bus multiplexed with 20-bit address bus Completely object code compatible with 8086 High performance and highly integrated system Components like DMA controller,clock generator,timer interrupt

controller and bus controller are integrated into single chip Seven new instructions added and two new operands types added to existing 8086 instructions Faster effective address calculation, improvement in the execution speed of many instructions

80186 BLOCK DIAGRAM

80286
Key Features 16-bit data bus 24-bit non-multiplexed address bus Packaged in a 68-pin ceramic pack 80286 has 2 24 = 16 M Byte of physical memory accessibility The first Intel processor that could run all the software written for its predecessor 6-byte pre-fetch queue+additional 3-byte decoded instruction queue 8086, 8088 can only operate in the real mode This mode allows the microprocessor to address only the first 1MB of

memory
The performance is 5 times faster than 8086

Basic Architecture of 80286

Consists of four functional blocks:

1. Address Unit: computes the physical address

2. Bus Unit: performs all memory and I/O reads and writes, prefetches instruction bytes, and controls transfer of data to and from processor extension devices such as the 80287 math coprocessor 3. Instruction Unit: fully decodes up to three prefetched instructions

and holds them in a queue, where the execution unit can access them.
This is a further example of how modern processors keep several instructions in the pipeline instead of waiting to finish one instruction before fetching the next 4. Execution Unit: uses its 16-bit ALU to execute instructions it receives

from the instruction unit

The four signal pins we need to discuss here are used to interface with processor extensions such as the 80287-math coprocessor. The processor extension request (PEREQ) input pin will be asserted by a coprocessor to tell the 80286 to perform a data transfer to or from memory for it. When the 80286 get around to do the transfer, it asserts the processor extension acknowledgement (PEACK) signal to the coprocessor to let it know the data transfer has started. The BUSY signal input on the 80286 functions the same way as the TEST input does on the 8086. When the 80286 execute a WAIT instruction, it will remain in a WAIT loop until it finds the BUSY signal from the coprocessor high. If a coprocessor finds some error during processing, it will assert the ERROR input of the 80286

Real mode memory:

The first 1MB of memory

Segment address + Offset address Segment address (The beginning address of any 64KB memory segment)

Protected Virtual Addressing Mode (PVAM) In this we have 1 GByte of virtual memory and 16 Mbyte of physical memory In this mode Address Unit acts as a complete MMU The address is 24 bit

To enter PVAM mode, Processor Status Word (PSW) is loaded by the instruction LPSW
Hardware reset is the only way to come out of protected mode Descriptor decides the memory segments location, length, and access rights

Here processor use a look-up table to compute physical address

This concept of mapping physical address uses descriptor and selector

Selector is a 32-bit register consisting of two parts: LSB 16-bits are used as an offset and MSB 16-bits are used to point to an array of descriptors Descriptor is an array consisting of 8-bytes and use to index a

segment.
Content from descriptor array provides the starting address of the segment. This starting address is then added to the 16-bit LSB offset

from selector to obtain the physical address

Protected Virtual Mode Addressing

LOGICAL ADDRESS SELECTOR
SEGMENT BASE ADDRESSES

OFFSET
CONTROL & PROTECTION BITS

DESCRIPTOR TABLE

PHYSICAL ADDRESS

Memory Bank of 80286

Supports eight addressing modes to access the operands stored in memory. Register Operand Mode Immediate Operand Mode Direct Mode Register Mode Based Mode Indexed Mode Based Indexed Mode Based Indexed Mode with Displacement

The 80286 supports the following seven data types 1. Integer : 8-bit or 16-bit signed binary operands using 2s complement representation. 2. Ordinal : 8-bit or 16-bit unsigned numeric value in binary. 3. Pointer : 32-bit pointers consisting of two 16-bit parts for segment selector and offset. 4. String: A data string of maximum 64K bytes or 32K words. 5. ASCII : Different characters in ASCII standard. 6. BCD : BCD representations and operations on decimal digits 0-9. 7. Packed BCD: Two digit decimal number represented by using BCD symbols

80286 Interrupt Handling

Real addressing mode has 256 interrupts with types 0-255. Each interrupt takes 4 bytes, so we have to reserve 1KByte of memory for interrupt In PVAM mode also we have 256 interrupts but it is not assigned a fixed memory. The interrupt descriptor table can be anywhere in the physical memory. Base address of interrupt descriptor table is stored in interrupt descriptor table register (IDTR). The particular descriptor is accessed as follows (Interrupt Type * 8) + IDTR Descriptor

80386
32 bit processor having 32 bit address bus and 32 bit data bus

Address 4GB of physical memory and 64 terabyte virtual memory

using memory caching concept(refresh the concept of cache memory). Apart from memory segmentation it also has a memory paging system which enables it to organize the available physical memory in terms of pages of 4K under segmented memory. Can work in scaled mode. In scaled mode any of the index register is multipied by a scale factor of 1,2,4 and 8 to obtain the displacement.

speed upto 33MHz.

 Has eight 32-bit general purpose registers which can be used as 8-bit
or 16-bit registers, six segment registers and 32-bit IP register. The flag register of 80386 is 32-bit long. It also has eight debug registers for hardware debugging. Apart from all the addressing modes of 8086 , 80386 has an additional scaled mode option: Scaled indexed mode: contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

Based Scaled indexed mode: contents of an index register are

multiplied by a scale factor and then added to base register to get the offset.

Based Scaled indexed mode with displacement: contents of an index

register are multiplied by a scale factor and then added to base register and a displacement to get the offset of an operand. The Internal Architecture of 80386 is divided into 3 sections. Central processing unit(CPU) Memory management unit(MMU) Bus interface unit(BIU)

Central processing unit is further divided into

Execution unit(EU) and Instruction unit(IU)

The Memory management unit consists of

Segmentation unit and Paging unit.

Segmentation unit allows the use of two address components, viz. segment and offset for relocability and sharing of code and data.
Segmentation unit allows segments of size 4Gbytes at max. The Paging unit organizes the physical memory in terms of pages of 4kbytes size each. Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages. The virtual memory is also organizes in terms of segments and pages by the memory management unit.

Register Organisation:
The 80386 has eight 32 - bit general purpose registers which may be used as either 8 bit or 16 bit registers. A 32 - bit register known as an extended register, is represented by the register name with prefix E. Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc. The 16 bit registers BP, SP, SI and DI in 8086 are now available with their extended size of 32 bit and are names as EBP,ESP,ESI and EDI.

AX represents the lower 16 bit of the 32 bit register EAX.

BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent 16 bit registers.

The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS.
The CS and SS are the code and the stack segment registers respectively, while DS, ES,FS, GS are 4 data segment registers. A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP.

Flag Register of 80386: The Flag register of 80386 is a 32 bit

register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extra new flags are added to the 80286 flag to derive the flag register of 80386. They are VM and RF flags.

 VM - Virtual Mode Flag: If this flag is set, the 80386 enters the

virtual 8086 mode within the protection mode. This is to be set only
when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception 13 is generated. This bit can be

set using IRET instruction or any task switch operation only in the
protected mode. RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions.

Memory Addressing in Real Mode: In the real mode, the 80386 can address at the most1Mbytes of physical memory using address lines A0-A19. Paging unit is disabled in real addressing mode, and hence the real addresses are the same as the physical addresses.

To form a physical memory address, appropriate segment registers contents (16-bits) are shifted left by four positions and then added to the 16-bit offset address formed using one of the addressing modes, in the same way as in the 80386 real address mode.
The segment in 80386 real mode can be read, write or executed, i.e. no protection is available.

Any fetch or access past the end of the segment limit generate exception 13 in real address mode.

The segments in 80386 real mode may be overlapped or nonoverlapped.

The interrupt vector table of 80386 has been allocated 1Kbyte space starting from 00000H to 003FFH. Protected Mode of 80386: All the capabilities of 80386 are available for utilization in its protected mode of operation. The 80386 in protected mode support all the software written for 80286 and 8086 to be executed under the control of memory management and protection abilities of 80386.

The protected mode allows the use of additional instruction, addressing modes and capabilities of 80386.

ADDRESSING IN PROTECTED MODE: In this mode, the contents of

segment registers are used as selectors to address descriptors which contain the segment limit, base address and access rights byte of the segment. The effective address (offset) is added with segment base address to calculate linear address. This linear address is further used as physical address, if the paging unit is disabled, otherwise the paging unit converts the linear address into physical address.

The paging unit is a memory management unit enabled only in protected mode. The paging mechanism allows handling of large segments of memory in terms of pages of 4Kbyte size.
The paging unit operates under the control of segmentation unit. The paging unit if enabled converts linear addresses into physical address, in protected mode.

Paging:
Paging Operation: Paging is one of the memory management techniques used for virtual memory multitasking operating system.
The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages. The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program. The pages are just fixed size portions of the program module or data. The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time.

Only a few pages of the segments, which are required currently for the execution need to be available in the physical memory. Thus the memory requirement of the task is substantially reduced, relinquishing the available memory for other tasks. Whenever the other pages of task are required for execution, they may be fetched from the secondary storage. The previous page which are executed, need not be available in the memory, and hence the space occupied by them may be relinquished for other tasks. Thus paging mechanism provides an effective technique to manage the physical memory for multitasking systems.

80486
The 32-bit 80486 is the next evolutionary step up from the 80386. One of the most obvious feature included in a 80486 is a built in math coprocessor. This coprocessor is essentially the same as the 80387 processor used with a 80386, but being integrated on the chip allows it to execute math instructions about three times as fast as a 80386/387 combination. 80486 is an 8Kbyte code and data cache. To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid array package instead of the 132 pin PGA used for the 80386.

GENERAL PURPOSE REGISTERS 31 16 15 0 AX BX CX EAX EBX ECX EDX ESI EDI EBP ESP

DX
SI DI BP SP SEGMENT REGISTERS

CS SS DS ES FS GS

CODE SEGMENT STACK SEGMENT

DATA SEGMENT

INSTRUCTION POINTER AND FLAG REGISTER 31 16 15 0 IP FLAGS EIP EFLAGS

Next page

Flag Register of 80486

FLAGS

31 E F L A G RESERVED FOR INTEL

18 17

16

15

14

13

12

11

10

AC

VM

RF

NT

IOPL

OF

DF

IF

TF

SF

ZF

AF

PF

CF

CF: Carry Flag AF: Auxiliary carry ZF: Zero Flag SF : Sign Flag TF : Trap Flag IE : Interrupt Enable AC : Alignment Check DF : Direct Flag OF : Over Flow IOPL : I/O Privilege Level NT : Nested Task Flag RF : Resume Flag VM : Virtual Mode

CACHE MEMORY: The cache memory system stores data used by a program and also the instructions of the program. The cache is organised as a 4 way set associative cache with each location containing 16 bytes or 4 doublewords of data.
Control register CR0 is used to control the cache with two new control bits not present in the 80386 microprocessor.

31

16

15

PG

CE

WT

AM

W P

NE

T S

E M

MP

PE

Control Register Zero ( CR0)For The 80486 Microprocessor

80486 Memory Management

The 80486 contains the same memory-management system as the 80386. This includes a paging unit to allow any 4K byte block of physical memory to be assigned to any 4K byte block of linear memory. The only difference between 80386 and 80486 memory-management system is paging. The 80486 paging system can disabled caching for section of translation memory pages, while the 80386 could not. If these are compared with 80386 entries, the addition of two new control bits is observed ( PWT and PCD ). The page write through and page cache disable bits control caching.

Intel Pentium Processor

The introduction of Pentium in 1993 brought the end of its x86 nomenclature.
This chip contains around 3 million transistors in it. The speeds varied from 90-133 MHz , of course the original product ran at 60-66 MHz. The Pentium was a Superscalar processor. The Pentium processor still has CISC architecture, but the high performance is achieved by using many if the organizational features of RISC architecture. Added a second execution pipeline to achieve superscalar performance. Branch prediction has added.

Introduced to market on March 22, 1993 with a CPU clock cycle of 66 Mhz
With its coming, it hosted many innovations, the most notable being: Superscalar architecture Dynamic Branch Prediction Pipelined Integer Unit Pipelined Floating-Point Unit These features made the newly introduced chip a very popular choice for desktop, although it was later found that the processor had some notorious implementation errors. The Integer unit has two pipelines(U and V),while the Floating Point Unit (FPU) has one pipeline.

Pipelined Integer Unit

The Pentium pipelined Integer Unit supports 5 stages: 1) Pre-fetch

2) Decode
3) Address generate 4) EX Execute - ALU and Cache Access 5) WB Writeback In the Pre-fetch cycle, two pre-fetch buffers read instructions to be executed. Instructions can be fetched from the U or V pipeline. The U pipeline contains more complex instructions. In the Decode cycle, two decoders, decode the instructions and try to pair them together so they can run in parallel, since the Pentium features a Superscalar architecture

Even though the Pentium processor features a Superscalar

architecture, in order for two instructions to run concurrently, like in

the diagram below, they need to satisfy some rules. Essentially, the instructions have to be independent otherwise they cannot be paired

together.
In the second Decode stage, or the address generate stage, the addresses of memory operands are calculated. After these calculations, the EX stage of the pipeline is ready to execute.

A Floating Point instruction cannot be paired with an Integer

instruction

 In the Execution cycle, the ALU is reached.

In the Write Back cycle, information is written back to the registers. For two instructions to be paired together in the Decode stage, they have to lack dependencies.The two paired instructions would also have to be basic, in the sense that they contain no displacements or immediate addressing. As it can be deduced, pipelines will sometimes execute an instruction at the time, despite the Superscalar ability. If two instructions are executing concurrently in the pipeline (given

they satisfy the

proper conditions, and are independent) and one of them stalls as a result of hazard control, the other one will also stall

Branch Prediction
The branch prediction mechanism is done through a branch target buffer. The branch target buffer contains the information about all branches. The prediction of whether a jump will occur or no, is based on the branchs previous behavior. There are four possible states that depict a branchs disposition to jump:
Stage 0: Very unlikely a jump will occur Stage 1: Unlikely a jump will occur Stage 2: Likely a jump will occur Stage 3: Very likely a jump will occur

When a branch has its address in the branch target buffer, its behavior is tracked.
This diagram portrays the four stages associated branch prediction.
If a branch doesnt jump two times in a row, it will go down to State 0. Once in Stage 0, the algorithm wont predict another another jump unless the branch will jump for two consecutive jumps (so it will go from State 0 to State 2)

Once in Stage 3, the algorithm wont predict another nojump unless the branch is not taken for two consecutive times

The Pentium processor has two primary operating modes and a "system

management mode. These modes are:

1.Protected Mode This is the native state of the microprocessor. In this mode all instructions and architectural features are available, providing the highest performance and capability. This is the recommended mode that all new applications and operating systems should target. Among the capabilities of protected mode is the ability to directly execute "realaddress mode" 8086 software in a protected, multi-tasking environment. This feature is known as Virtual-8086 "mode" (or "V86 mode"). Virtual-8086 "mode" however, is not actually a processor "mode," it is in fact an attribute which can be enabled for any task (with appropriate software) while in protected mode

Real-Address Mode (also called "real mode") This mode provides the programming environment of the Intel 8086 processor, with a few extensions (such as the ability to break out of this mode). Reset initialization places the processor in real mode where, with a single instruction, it can switch to protected mode.
System Management Mode The Pentium microprocessor also provides support for System Management Mode (SMM). SMM is a standard architectural feature unique to all new Intel microprocessors, beginning with the Intel386 SL processor, which provides an operating-system and application independent and transparent mechanism to implement system power management and OEM differentiation features. SMM is entered through activation of an external interrupt pin (SMI#), which switches the CPU to a separate address space while saving the entire context of the CPU. SMM-specific code may then be executed transparently. The operation is reversed upon returning.

Branch Target Buffer: The Pentium processor fetches the branch target

instruction before it executes the branch instruction.

Dual 8-KB On-Chip Caches: The Pentium processor has two separate 8-

kilobyte (KB) caches on chip--one for instructions and one for data-which allows the Pentium processor to fetch data and instructions from the cache simultaneously. Write-Back Cache: When data is modified; only the data in the cache is

changed. Memory data is changed only when the Pentium processor

replaces the modified data in the cache with a different set of data

64-Bit Bus: With its 64-bit-wide external data bus (in contrast to the

Intel486 processor's 32-bit- wide external bus) the Pentium processor

can handle up to twice the data load of the Intel486 processor at the same clock frequency. Instruction Optimization: The Pentium processor has been

optimized to run critical instructions in fewer clock cycles than the

Intel486 processor. Floating-Point Optimization: The Pentium processor executes

individual instructions faster through execution pipelining, which

allows multiple floating-point instructions to be executed at the same time.

Pentium Extensions: The Pentium processor has fewer instruction set extensions than the Intel486 processors. The Pentium processor also has a set of extensions for multiprocessor (MP) operation. This makes a computer with multiple Pentium processors possible. Register set The purpose of the Register is to hold temporary results, and control the execution of the program. General-purpose registers in Pentium are EAX, ECX, EDX, EBX, ESP, EBP,ESI, or EDI.

The 32-bit registers are named with prefix E, EAX, etc, and the least 16 bits 0-15 of these registers can be accessed with names such as AX, SI Similarly the lower eight bits (0-7) can be accessed with names such as AL & BL. The higher eight bits (8-15) with names such as AH & BH. The instruction pointer EAP known as program counter(PC) in 8bit microprocessor, is a 32-bit register to handle 32-bit memory addresses, and the lower 16 bit segment IP is used for 16-bi memory address.

The flag register is a 32-bit register , however 14-bits are being used at present for 13 different tasks; these flags are upward compatible with those of the 8086 and 80286. The comparison of the available flags in 16-bit and 32-bit microprocessor is may provide some clues related to capabilities of these processors. The 8086 has 9 flags, the 80286 has 11 flags, and the 80286 has 13 flags. All of these flag registers include 6 flags related to data conditions (sign, zero, carry, auxiliary, carry , overflow, and parity) and three flags related to machine operations.(interrupts, Single-step and Strings). The 80286 has two additional : I/O Privilege and Nested Task. The I/O Privilege uses two bits in protected mode to determine which I/O instructions can be used, and the nested task is used to show a link between two tasks. The processor also includes control registers and system address registers , debug and test registers for system and debugging operations

Newer Generation Chips

The next move up from Pentium was Pentium MMX. The Pentium MMX, includes new instructions, registers, and data types which are aimed at maximizing the speed of multimedia computations. Since multimedia work requires massive data manipulation, SIMD

instructions were added to the MMX set. SIMD instructions work on

multiple data values at once, in order to maximize the amount of work done by each instruction

The improved multimedia support of the MMX, along with lower power
consumption, larger caches, and new branch prediction mechanisms, brought about the new generations of Pentiums (II & III)