Analog Digital VLSI Design

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Why should designer know fab?

Design performance varies after fab. Due to process variationsDimensions vary due to shifting of masks, Dopants diffusing beneath the masks, Undercutting during wet etching. Hence MOS parameters like gm, W, L, ID varies . So we have to design with margins.

Lateral diffusion

Under cutting

CMOS Manufacturing Process

CMOS processing
N-WELL P-WELL TWIN-TUB, TRIPLE WELL SOI

Wafer preparation
Defect free single crystalline lightly doped WAFER. Metallurgical grade silicon-electronic grade silicon(99.99% pure) Single crystalline structure obtained by melting and then cooling ---Czochralski method Ingot cut into wafers using diamond saw Wafers are than polished to mirror finish

Process involved
Photolithography Deposition Oxidation Etching Diffusion/ion implantation

CMOS Process
cross sectional diagram n well process

Lithography
Lithography: process used to transfer patterns to each layer of the IC Lithography sequence steps: Designer:
Drawing the layer patterns on a layout editor

Silicon Foundry:
Masks generation from the layer patterns in the design data base Printing: transfer the mask pattern to the wafer surface Process the wafer to physically pattern each layer of the IC

Lithography
Basic sequence
The surface to be patterned is:
spin-coated with photoresist the photoresist is dehydrated in an oven (photo resist: light-sensitive organic polymer)
1. Photoresist coating Photoresist

SiO2 Substrate 2. Exposure Opaque Ultra violet light

Mask Unexposed Exposed

The photo-resist is exposed to ultra violet light:

For a positive photoresist exposed areas become soluble and non exposed areas remain hard

Substrate 3. Development

The soluble photo-resist is chemically removed (development).

The patterned photoresist will now serve as an etching mask for the SiO2

Substrate

1. Photoresist coating Photoresist

SiO2 Substrate 2. Exposure Opaque Ultra violet light

Mask Unexposed Exposed

Substrate 3. Development

Substrate

Lithography
The SiO2 is etched away leaving the substrate exposed:
the patterned resist is used as the etching mask
4. Etching

Ion Implantation:
the substrate is subjected to highly energized donor or acceptor atoms The atoms impinge on the surface and travel below it The patterned silicon SiO2 serves as an implantation mask

Substrate 5. Ion implant

Substrate 6. After doping

The doping is further driven into the bulk by a thermal cycle

diffusion

Substrate

4. Etching

Substrate 5. Ion implant

Substrate 6. After doping

diffusion

Substrate

Lithography
The lithographic sequence is repeated for each physical layer used to construct the IC. The sequence is always the same:
Photo-resist application Printing (exposure) Development Etching

Lithography
Patterning a layer above the silicon surface
1. Polysilicon deposition Polysilicon 4. Photoresist development

SiO2 Substrate 2. Photoresist coating photoresist Substrate 5. Polysilicon etching

Substrate 3. Exposure UV light

Substrate

6. Final polysilicon pattern

Substrate

Substrate

Lithography
Etching:
Process of removing unprotected material Etching occurs in all directions Horizontal etching causes an under cut preferential etching can be used to minimize the undercut
anisotropic etch (ideal) resist layer 1 layer 2

isotropic etch undercut

resist layer 1 layer 2

Etching techniques:
Wet etching: uses chemicals to remove the unprotected materials Dry or plasma etching: uses ionized gases rendered chemically active by an rf-generated plasma

preferential etch undercut

resist layer 1 layer 2

Physical structure

NMOS physical structure:

p-substrate n+ source/drain gate oxide (SiO2) polysilicon gate CVD oxide metal 1 Leff< Ldrawn (lateral doping effects)

NMOS layout representation: Implicit layers:

oxide layers substrate (bulk)

Drawn layers:
n+ regions polysilicon gate oxide contact cuts, metal layers

Physical structure

Layout representation

Schematic representation

CVD oxide Metal 1 Poly gate Source Ldrawn

Drain

Ldrawn

n+

n+ Leffective

W drawn

S B

Gate oxide
p-substrate (bulk)

Physical structure

PMOS physical structure:

p-substrate n-well (bulk) p+ source/drain gate oxide (SiO2) polysilicon gate CVD oxide, metal 1

PMOS layout representation: Implicit layers:

oxide layers

Drawn layers:
n-well (bulk) n+ regions polysilicon gate, oxide contact cuts, metal layers

Physical structure

Layout representation

Schematic representation

CVD oxide Metal 1 Poly gate

Source

Ldrawn

Drain

Ldrawn S

G
D B

p+

p+ Leffective n-well

W drawn

Gate oxide n-well (bulk)

p-substrate

VDD

M2 Vin
V

M1

vin
gnd vdd

vout

Layout

vdd

gnd

CMOS fabrication sequence

0. Start:
For an n-well process the starting point is a p-type silicon wafer: wafer: typically 75 to 230mm in diameter and less than 1mm thick

1. Epitaxial growth:
A single p-type single crystal film is grown on the surface of the wafer by:
subjecting the wafer to high temperature and a source of dopant material
p-epitaxial layer Diameter = 75 to 230mm P+ -type wafer The epi layer is used as the base layer to build the devices< 1mm

CMOS fabrication sequence

2. N-well Formation:
PMOS transistors are fabricated in n-well regions The first mask defines the n-well regions N-wells are formed by ion implantation or deposition and diffusion Lateral diffusion limits the proximity between structures Ion implantation results in shallower wells compatible with todays fine-line processes
Physical structure cross section n-well mask Lateral diffusion Mask (top view)

n-well p-type epitaxial layer

4. Etching

Substrate 5. Ion implant

Substrate 6. After doping

diffusion

Substrate

N well mask

CMOS fabrication sequence

3. Active area definition:
Active area:
planar section of the surface where transistors are build defines the gate region (thin oxide) defines the n+ or p+ regions

A thin layer of SiO2 is grown over the active region and covered with silicon nitride

Stress-relief oxide

Silicon Nitride

Active mask

n-well p-type

Active mask

CMOS fabrication sequence

4. Isolation:
Parasitic (unwanted) FETs exist between unrelated transistors (Field Oxide FETs)

Field Oxide Growth

Impact of FOX- parasitic MOS

We have Source and drains are existing source and drains of wanted devices Second layer is Field oxide Gates are metal and polysilicon interconnects on top of Fox Parastic MOS should not conduct So, the threshold voltage of FOX FETs should be higher.

Parasitic FOX device

n+

n+

n+

n+

p-substrate (bulk)

CMOS fabrication sequence

FOX FETs threshold is made high by:
introducing a channel-stop diffusion that raises the impurity concentration in the substrate in areas where transistors are not required making the FOX thick

4.1 Channel-stop implant

The silicon nitride (over n-active) and the photoresist (over n-well) act as masks for the channel-stop implant
channel stop mask = ~(n-well mask) resit

Implant (Boron)

n-well p-type p+ channel-stop implant

CMOS fabrication sequence

4.2 Local oxidation of silicon (LOCOS)
The photoresist mask is removed The SiO2/SiN layers will now act as a masks The thick field oxide is then grown by:
exposing the surface of the wafer to a flow of oxygen-rich gas

The oxide grows in both the vertical and lateral directions This results in a active area smaller than patterned

patterned active area

Field oxide (FOX)

n-well
active area after LOCOS

p-type

CMOS fabrication sequence

Silicon oxidation is obtained by:
Heating the wafer in a oxidizing atmosphere:
Wet oxidation: water vapor, T = 900 to 1000C (rapid process)

Oxidation consumes silicon

SiO2 has approximately twice the volume of silicon The FOX is recedes below the silicon surface by 0.46XFOX

Field oxide
XFOX 0.54 XFOX 0.46 XFOX

Silicon surface

Silicon wafer

CMOS fabrication sequence

5. Gate oxide growthDry oxidation: Pure oxygen, T = 1200C (high temperature required to achieve an acceptable growth rate). Slow process
The nitride and stress-relief oxide are removed The devices threshold voltage is adjusted by:
adding charge at the silicon/oxide interface

The well controlled gate oxide is grown with thickness tox

n-well p-type tox Gate oxide n-well p-type tox

CMOS fabrication sequence

6. Polysilicon deposition and patterning
A layer of polysilicon is deposited over the entire wafer surface The polysilicon is then patterned by a lithography sequence All the MOSFET gates are defined in a single step The polysilicon gate can be doped (n+) while is being deposited to lower its parasitic resistance (important in high speed fine line processes)
Polysilicon mask Polysilicon gate

n-well p-type

Poly mask

Undercutting

CMOS fabrication sequence

7. NMOS formation
Photoresist is patterned to define the n+ regions Donors (arsenic or phosphorous) are ion-implanted to dope the n+ source and drain regions The process is self-aligned The gate is n-type doped
n+ implant (arsenic or phosphorous) n+ mask

n-well Photoresist p-type

N+ diffusion mask

CMOS fabrication sequence

8. PMOS formation
Photoresist is patterned to cover all but the p+ regions A boron ion beam creates the p+ source and drain regions The polysilicon serves as a mask to the underlying channel This is called a self-aligned process It allows precise placement of the source and drain regions During this process the gate gets doped with p-type impurities
Since the gate had been doped n-type during deposition, the final type (n or p) will depend on which dopant is dominant
p+ implant (boron) p+ mask

n-well Photoresist p-type

P+ diffusion mask

CMOS fabrication sequence

9. Annealing
After the implants are completed a thermal annealing cycle is executed This allows the impurities to diffuse further into the bulk After thermal annealing, it is important to keep the remaining process steps at as low temperature as possible

n-well n+ p+ p-type

CMOS fabrication sequence

10. Contact cuts
The surface of the IC is covered by a layer of CVD oxide
The oxide is deposited at low temperature (LTO) to avoid that underlying doped regions will undergo diffusive spreading

Contact cuts are defined by etching SiO2 down to the surface to be contacted These allow metal to contact diffusion and/or polysilicon regions
Contact mask

n-well n+ p+ p-type

Contact- cut mask

CMOS fabrication sequence

11. Metal 1
A first level of metallization is applied to the wafer surface and selectively etched to produce the interconnects

metal 1

metal 1 mask

n-well n+ p+ p-type

Metal mask

CMOS fabrication sequence

12. Metal 2
Another layer of LTO CVD oxide is added Via openings are created Metal 2 is deposited and patterned

Via

metal 2 metal 1

n-well n+ p+ p-type

CMOS fabrication sequence

13. Over glass and pad openings
A protective layer is added over the surface: The protective layer consists of:
A layer of SiO2 Followed by a layer of silicon nitride

The SiN layer acts as a diffusion barrier against contaminants (passivation) Finally, contact cuts are etched, over metal 2, on the passivation to allow for wire bonding.

Wire bonding pad structures

Micro photograph of fabricated chip

Circuit Under Design

VDD M2 M4 Vin Vout Vout2 VDD

M1

M3

This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.

Circuit Layout

vdd

gnd

Start Material
A

Starting wafer: n-type with doping level = 10 13/cm3 * Cross-sections will be shown along vertical line A-A

N-well Construction

(1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist

N-well Construction

(4) Expose resist using n-well mask

N-well Construction

(5) Develop resist (6) Etch nitride and (7) Grow thick oxide

N-well Construction

(8) Implant n-dopants (phosphorus) (up to 1.5 mm deep)

P-well Construction

Repeat previous steps

Grow Gate Oxide

0.055 mm thin

Grow Thick Field Oxide

0.9 mm thick

Uses Active Area mask Is followed by threshold-adjusting implants

Polysilicon layer

Source-Drain Implants

n+ source-drain implant (using n+ select mask)

Source-Drain Implants

p+ source-drain implant (using p+ select mask)

Contact-Hole Definition

(1) Deposit inter-level dielectric (SiO2) 0.75 mm

(2) Define contact opening using contact mask

Aluminum-1 Layer

Aluminum evaporated (0.8 mm thick) followed by other metal layers and glass

Advanced Metalization