Scribd
Upload
127 views

Timing Control

1) Verilog provides various timing controls including delay controls using # symbols to specify delays, event controls using @ symbols to trigger execution based on events, and wait statements to delay execution until a condition is true. 2) Delay controls allow specifying delays between statement executions using constants, parameters, or expressions while event controls allow triggering execution based on signal value changes like posedge, negedge, or named events. 3) Delay back-annotation is used in the design flow where preliminary delay estimates are replaced by actual post-layout delay values to get a more accurate timing analysis of the gate-level design.

Uploaded by

Balaramkishore Gangireddy
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
127 views

Timing Control

1) Verilog provides various timing controls including delay controls using # symbols to specify delays, event controls using @ symbols to trigger execution based on events, and wait statements to delay execution until a condition is true. 2) Delay controls allow specifying delays between statement executions using constants, parameters, or expressions while event controls allow triggering execution based on signal value changes like posedge, negedge, or named events. 3) Delay back-annotation is used in the design flow where preliminary delay estimates are replaced by actual post-layout delay values to get a more accurate timing analysis of the gate-level design.

Uploaded by

Balaramkishore Gangireddy
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 23

Timing control in verilog

Click to edit Master subtitle style

Module 3.1 Delays in Verilog

3/12/13

Procedural blocks and timing controls.


Delay

controls. Event controls. Event controls-Wait

Edge-Sensitive Level-Sensitive

statements.
Named

Events.

3/12/13

Timing Controls
Delay-Based

Regular delay control AKA Inertial Delay Intra-assignment delay control AKA Transport delay Zero delay control 3/12/13

Regular Delay Control


parameter latency = 20; parameter delta = 2; regx,y,z,p,q; Initial Begin
x=0; // no delay control #10 y = 1; //delay control with a constant #latency z = 0; //delay control with identifier #(latency + delta) p = 1; //delay control with expression #y x = x + 1; //delay control with identifier
3/12/13

Intra-assignment delay control


Assigning

delay to the right of the assignment operator intra-assignment delay computes the right-hand-side expression at the current time and defer the assignment of the computed value to the left-hand-side variable. to regular delays with a temporary variable to store the current value of a right-hand-side expression
3/12/13

The

Equivalent

Intra-assignment Delay

3/12/13

Example 1

3/12/13

Example 2 : change in assignment

3/12/13

Example 3 : Ex1 + change in assignment

3/12/13

Zero delay control

3/12/13

Zero delay control

3/12/13

Timing Control
Verilog

is a discrete event time simulator. If there is no timing control, simulation time does not advance. Simulated time can only progress by one of the following:

gate or wire delay, if specified a delay control, introduced by the # symbol. an event control, introduced by the @ symbol. the wait statement.
3/12/13 order of execution of events in the

The

Delay based Timing Control


Delay

Control (#)

Expression specifies the time duration between initially encountering the statement and when the statement actually executes. Delay in Procedural Assignments
Inter-Statement Intra-Statement

Delay Delay Delay Delay

For example:
Inter-Statement

#10 A = A + 1;
Intra-Statement

A = #10 A + 1;

3/12/13

Event-Based Timing Control (cont.)


Events

(@)

Change in the value of a register or net Used to trigger execution of a statement or block (reactive behavior/reactivity)

Types

of Event-based timing control


Regular event control Named event control Event OR control
3/12/13

Event-Based Timing Control (cont.)


Regular

event control

Symbol: @(<event>) Events to specify:


posedge

sig:

Change of sig from any value to 1 or from 0 to any value

negedge

sig:

Change of sig from any value to 0 or from 1 to any value

sig:

Any chage in sig value


3/12/13

Event-Based Timing Control (cont.)


Regular

event control Examples:

@reg_a begin A = B&C; end

@(posedge clock1) A = B&C;

@(negedge clock2) A = B&C;

Forever @(negedge clock3) begin


3/12/13

Event-Based Timing Control (cont.)


Named

event control

You can declare (name) an event, and then trigger and recognize it. Verilog keyword for declaration: event
event

event1;

Verilog symbol for triggering: ->


->event1

Verilog symbol for recognizing: @()


@(event1)

begin

<some procedural statements> 3/12/13

end

Event-Based Timing Control (cont.)


Event

OR control

Used when need to trigger a block upon occurrence of any of a set of events. The list of the events: sensitivity list Verilog keyword: or Look at the handout

Event

OR control Example:

always @ ( reset or clock )


begin if ( reset ) q= 1b0; else 3/12/13

Timing Control (cont.)


wait

Statement

The wait statement allows a procedural statement or a block to be delayed until a condition becomes true. The difference between the behavior of a wait statement and an event is that the wait statement is level sensitive whereas @(posedge clock); is triggered by a signal transition or is edge sensitive. For Example:
wait

(A == 3)
3/12/13

begin

Delay Back-Annotation
Delay back- annotation is an important and vast topic in timing simulation. in this section, we introduce the designer to the concept of backannotation of delays in a simulation.

3/12/13

The various steps in the flow that use delay back-annotation are as follows: 1. The designer writes the RTL description and then performs functional simulation. 2. The RTL description is converted to a gate level netlist by a logic synthesis tool. 3. The designer obtains prelayout estimates of delays in the chip by using a delay calculator and information about the IC fabrication process. Then, the designer does timing simulation or static timing verification of the 3/12/13 gate-level netlist, using these preliminary

4. The gate-level netlist is then converted to layout by a place and route tool. The postlayout delay values are computed from the resistance (R) and capacitance (C) information in the layout. The R and C information is extracted from factors such as geometry and IC fabrication process. 5. The post-layout delay values are backannotated to modify the delay estimates for the gate-level netlist. Timing simulation or static timing verification is run again on the gate-level netlist to check if timing constraints are still satisfied.
3/12/13

Delay Back-Annotation

3/12/13

You might also like