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Lect3 Transistors

This document provides an overview of CMOS transistor theory, including: 1) It describes the MOS capacitor structure and its operating modes of accumulation, depletion, and inversion. 2) It explains the current-voltage characteristics of nMOS and pMOS transistors in the cutoff, linear, and saturation regions. The linear region current is derived based on channel charge and carrier mobility. 3) It discusses the gate, source, and drain capacitances of MOS transistors and how they impact speed. The gate capacitance is proportional to oxide capacitance and area, while diffusion capacitance at the source and drain is parasitic.

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Nitu Vlsi
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101 views

Lect3 Transistors

This document provides an overview of CMOS transistor theory, including: 1) It describes the MOS capacitor structure and its operating modes of accumulation, depletion, and inversion. 2) It explains the current-voltage characteristics of nMOS and pMOS transistors in the cutoff, linear, and saturation regions. The linear region current is derived based on channel charge and carrier mobility. 3) It discusses the gate, source, and drain capacitances of MOS transistors and how they impact speed. The gate capacitance is proportional to oxide capacitance and area, while diffusion capacitance at the source and drain is parasitic.

Uploaded by

Nitu Vlsi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Lecture 3:

CMOS
Transistor
Theory
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 2
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 3
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (AV/At) -> At = (C/I) AV
Capacitance and current determine speed
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 4
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
MOS Capacitor
Gate and body form MOS
capacitor
Operating modes
Accumulation
Depletion
Inversion
(b)
+
-
0 < V
g
< V
t
depletion region
(c)
+
-
V
g
> V
t
depletion region
inversion region
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 5
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s

V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
> 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 6
nMOS Cutoff
No channel
I
ds
0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 7
nMOS Linear
Channel forms
Current flows from d to s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 8
nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 9
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 10
Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversions
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 11
Carrier velocity
Charge is carried by e-
Electrons are propelled by the lateral electric field
between source and drain
E = V
ds
/L
Carrier velocity v proportional to lateral E-field
v = E called mobility
Time for carrier to cross channel:
t = L / v
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 12
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V

|
=
| |
=
|
\ .
| |
=
|
\ .
ox
=
W
C
L
|
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 13
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V
|
|
| |
=
|
\ .
=
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 14
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
|
|

<

| |
= <
|
\ .

>

Shockley 1
st
order transistor models
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 15
Example
We will be using a 0.6 m process for your project
From AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 A/V
100 10
ox
W W W
C
L L L
|

| |
| |
= = =
| |

\ .
\ .
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 16
pMOS I-V
All dopings and voltages are inverted for pMOS
Source is the more positive terminal
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/Vs in AMI 0.6 m process
Thus pMOS must be wider to
provide same current
In this class, assume

n
/
p
= 2
-5 -4 -3 -2 -1 0
-0.8
-0.6
-0.4
-0.2
0
I
d
s
(
m
A
)
V
gs
= -5
V
gs
= -4
V
gs
= -3
V
gs
= -2
V
gs
= -1
V
ds
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 17
Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 18
Gate Capacitance
Approximate channel as connected to source
C
gs
= c
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9c
0
)
polysilicon
gate
CMOS VLSI Design CMOS VLSI Design
4th Ed.
3: CMOS Transistor Theory 19
Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g

for contacted diff
C
g
for uncontacted
Varies with process

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