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8259 PIC: Intel's Prog. Interrupt Controller

The 8259 Programmable Interrupt Controller adds 8 prioritized interrupt requests to the microprocessor. It uses an Interrupt Request Register to store requested interrupts, an In-Service Register for interrupts currently being serviced, and a priority resolver to determine the highest priority interrupt. The 8259 has pins for interrupt requests and acknowledgment. It can be configured in master-slave mode to support up to 64 interrupts. Initialization and operation commands program the 8259 by setting interrupt masks and vectors.

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Asawari Dudwadkar
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215 views22 pages

8259 PIC: Intel's Prog. Interrupt Controller

The 8259 Programmable Interrupt Controller adds 8 prioritized interrupt requests to the microprocessor. It uses an Interrupt Request Register to store requested interrupts, an In-Service Register for interrupts currently being serviced, and a priority resolver to determine the highest priority interrupt. The 8259 has pins for interrupt requests and acknowledgment. It can be configured in master-slave mode to support up to 64 interrupts. Initialization and operation commands program the 8259 by setting interrupt masks and vectors.

Uploaded by

Asawari Dudwadkar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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8259

Programmable Interrupt Controller


By

Asawari Dudwadkar
Dept. of Electronics VESIT
asawari 2012

8259 architecture

asawari 2012

8259 Architecture
IRR [ Interupt request register] store all int levels requesting service ISR In service register stores int levels being serviced. Priority resolver determines priority of bits set in IRR, highest priority bit selected & strobed into ISR during Int acknowledge.
IMR Int mask register- stores int lines to be masked.
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Pins of 8259

8259 adds 8 vectored priority encoded interrupts to the microprocessor. It can be expanded to 64 interrupt requests by using one master 8259A and 8 slave units.
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INT Connects to the INTR pin on the microprocessor. INTA Connects to the INTA pin on the microprocessor. A0 Selects different command words in the 8259A. CS Chip select - enables the 8259A SP/EN- Slave Program (1 for master, 0 for slave) / Enable Buffer (controls the data bus transreceivers when in buffered mode). CAS2-CAS0 - Used as outputs from the master to the slaves in cascaded systems.

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Single 8259 connected to 8086

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A single 8259A connected with the 8086

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Master Slave mode

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2, 8259 connected in master Slave mode

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Programming 8259

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Initialization sequence

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Programming the 8259A


Programmed by Initialization (ICWs) and Operation (OCWs) Command Words. There are 4 ICWs. At power-up, ICW1, ICW2 and ICW4 must be sent. If ICW1 indicates cascade mode, then ICW3 must also be sent.
ICW

LTIM indicates if IRQ lines are positive edge-triggered or leveltriggered.

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ICW 2

oThese bits determine the vector numbers used with the IRQ inputs. For example, if programmed to generate vectors 08H-0FH, 08H is placed into these bit positions. oA8 A15 interrupt vector address of 8085
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ICW 3

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ICW 4

oFully nested mode allows the highest-priority interrupt request from a slave to be recognized by the master while it is processing another interrupt from a slave.

oIf AEOI = 1, it indicates that an interrupt automatically resets the interrupt request bit, otherwise OCW2 is consulted for
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Operation Command word OCW

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oCW1 is used to read or set the interrupt mask


register. If a bit is set, it will mask the corresponding interrupt input

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OCW2: Only programmed when the AEOI mode


in ICW4 is 0.

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Ocw 2
Non-specific

EOI: Here, the ISR sets this bit to indicate EOI. The 8259A automatically determines which interrupt was active and re-enables it and lower priority interrupts. Specific EOI: ISR resets a specific interrupt request given by L2-L0. Rotate commands cause priority to be rotated w.r.t. the current one being processed. Set priority: allows the setting of the lowest priority interrupt (L2-L0).

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Ocw 3

If polling is set, the next read operation will read the polled word. If the leftmost bit is set in the poll word, the rightmost 3 bits indicate the active interrupt request with highest priority.

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ISR update procedure with rotating


priority configured.

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