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Lecture 4 S110

1. Verilog HDL allows designing sequential logic circuits using finite state machines (FSM). 2. The process involves defining the states, inputs, outputs, and state transitions of the FSM using a state table or diagram. 3. Verilog allows implementing FSMs using always blocks, case statements, and registers to describe the state transitions and outputs.

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34 views21 pages

Lecture 4 S110

1. Verilog HDL allows designing sequential logic circuits using finite state machines (FSM). 2. The process involves defining the states, inputs, outputs, and state transitions of the FSM using a state table or diagram. 3. Verilog allows implementing FSMs using always blocks, case statements, and registers to describe the state transitions and outputs.

Uploaded by

cikghu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Verilog HDL

Traditional design flow of sequential logic circuit


Design specification Manual State Diagram Manual State Table Manual

In = Clock, Reset, Input ... Out = X, Y Machine State = S1, S2

Boolean Exp and Simplified


Manual Implement on several ICs

GENERAL PROCEDURE FOR DESIGNING SYNCHRONOUS CIRCUIT


1. Understand the specifications of the sequential circuit. Determine the types and number of input and output terminals. Note: all CLK inputs of FF are connected to a common clock source. 2. Identify the number of states and determine the number of flip-flops used. Produce a State Diagram. 3. Translate the State Diagram into a State Table. Note: the values of Decoder States determine the changes from Present State to Next State. 4. Establish the Boolean Expressions for all decoders and output functions (with respect to Present State and Input State (if any) as variables. 5. Simplify the expressions using K-map or Boolean Algebra 6. Draw the logic circuit diagram.

Sequential Logic Circuit Implement by PLD Technology


Design specification In = Clock, Reset, Input ... Out = X, Y Machine State = S1, S2

Manual (programming)
Design description

HDL Syntax

Automatic
Implement on ONE CPLD/FPGA chip

Implementations of A Finite State Machine (FSM) Using Verilog

FSM Design Using Verilog


FSM is a computational model consisting of a finite number of states and transitions between those states, possibly with accompanying actions. [IEEE 610]

Standard model for a Finite State Machine

FSM Design Using Verilog


Example1: Consider the following State Diagram. Specifications: No of finite states = 6 (A, B, C, D, E and F) No of inputs = 1 No of outputs = 3

FSM Design Using Verilog

FSM Design Using Verilog

FSM Design Using Verilog


module fsm (input i, clock, reset, output reg [2:0] out); reg [2:0] currentState, nextState; localparam [2:0] A = 3'b000 B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100, F = 3'b101; The localparam statement specifies the state assignment for the system.

FSM Design Using Verilog

FSM Design Using Verilog

User Defined Primitives (UDPs)


Definition: UDP is a set of gate primitives specified and designed by the user. UDP can be either combinatorial or sequential.

Why UDP?

UDP is a very compact and efficient way of describing a possibly arbitrary block of logic UDP can reduce the pessimism with respect to the unknown x value in the simulators three valued logic, thus creating more realistic models for certain situations UDP can increase simulation efficiency

Creating UDP (Combinational Logic)


UDP are defined in a manner similar to a truth table enumeration of a logic function. UDP are defined outside modules. Started with keyword primitive followed by a UDP name and declarations of output and inputs (in bracket). A table (similar to a Truth Table) is then specified showing the value of the output for the various combinations of the inputs. A colon separates the output on its right from the inputs on its left Ended with keyword endprimitive.

Creating UDP (Combinational Logic)


There are a number of rules that must be considered:

Primitives can have multiple input ports, but exactly only one output port. They may not have bidirectional inout ports. The output port must be the first port in the port list. All primitive ports are scalar. No vector ports are allowed. Only logic values of 1, 0, and x are allowed on input and output. The z value cannot be specified, although on input, it is treated as an x.

Creating UDP (Combinational Logic) Example

Creating UDP (Sequential Logic) Level Sensitive


Sequential UDP are defined similar to the combinational logic with some differences:
1. The output shall also be declared as type reg to indicate there is an internal state. The output value is always the same as the value of internal state. 2. There is an additional field added in each table entry to indicate the current state. This field is separated by colons from the inputs and the output.

Creating UDP (Sequential Logic) Level Sensitive

Note: ? = 0,1 or x and - = no change of value

Creating UDP (Sequential Logic) Edge Sensitive


Similar to creating Level Sensitive Sequential Logic UDP, the edge sensitive UDP differs in the manner of:
1. Changes at the output triggers by specific transitions of the inputs such as clock Positive Going Transition (PGT) or Negative Going Transition (NGT). 2. All unspecified transitions will default to an output value x (unknown). All transitions must be explicitly specified to avoid output default to x.

Creating UDP (Sequential Logic) Edge Sensitive - Example

Creating UDP (Sequential Logic) Edge Sensitive with Initial - Example

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