Chapter 9 -- Simplification of Sequential Circuits

Redundant States in Sequential Circuits

Removal of redundant states is important because
Cost: the number of memory elements is directly related to the number of states Complexity: the more states the circuit contains, the more complex the design and implementation becomes Aids failure analysis: diagnostic routines are often predicated on the assumption that no redundant states exist

Equivalent States
States S1, S2, , Sj of a completely specified sequential circuit are said to be equivalent if and only if, for every possible input sequence, the same output sequence is produced by the circuit regardless of whether S1, S2, , Sj is the initial state. Let Si and Sj be states of a completely specified sequential circuit. Let Sk and Sl be the next states of Si and Sj, respectively for input Ip. Si and Sj are equivalent if and only if for every possible Ip the following are conditions are satisfied.
The outputs produced by Si and Sj are the same, The next states Sk and Sl are equivalent.

Equivalent States Illustration

x 0 A B x SC (a) z C D E C/1 C/1 B/1 D/0 E/0 1 B/0 E/0 E/0 B/1 A/1 (b) Initial Input Sequences State 000 001 010 011 100 101 A 111 110 100 101 011 010 B 111 110 100 101 000 001 C 111 110 100 101 000 001 D 000 001 011 010 111 110 E 000 001 011 010 111 110 (d) 110 111 000 011 011 100 101 001 010 010 101 100 Initial Input Sequences State 00 01 11 10 A 11 10 01 00 B 11 10 00 01 C 11 10 00 01 D 00 01 11 10 E 00 01 11 10 (c)

Figure 9.1

Equivalence Relations
Equivalence relation: let R be a relation on a set S. R is an equivalence relation on S if and only if it is reflexive, symmetric, and transitive. An equivalence relation on a set partitions the set into disjoint equivalence classes. Example: let S = {A,B,C,D,E,F,G,H} and R = {(A,A),(B,B),(B,H),(C,C),(D,D),(D,E),(E,E),(E,D),(F,F),(G,G),(H,H), (H,B)}. Then P = (A)(BH)(C)(DE)(F)(G) Theorem: state equivalence in a sequential circuit is an equivalence relation on the set of states. Theorem: the equivalence classes defined by the state equivalence of a sequential circuit can be used as the states in an equivalent circuit.

Methods for Finding Equivalent States

Inspection Partitioning Implication Tables

Finding Equivalent States By Inspection

x 0 A B C D B/0 C/0 D/1 C/0 (a) 1 C/1 A/1 B/0 A/1 A B C 0 B/0 C/0 B/1 (b) x A B C D 0 B/ 0 D/0 D/1 B/ 0 (e) 1 C/1 A/ 1 B/ 0 A/ 1 x 1 C/1 A/1 B/0 A B C D x 0
B/0 B/0

1 C/1
A/1 B/

x A B C 0 B/ 0 B/ 0 B/ 1 1 C/1 A/1 B/0 (d)

D/1 D/0 (c)

0 A/ 1

Figure 9.2

Finding Equivalent States by Partitioning

Partition P0 O utput for x = 0 O utput for x = 1 Partition P1 N state for x = 0 ext N state for x = 1 ext Partition P2 N state for x = 0 ext N state for x = 1 ext Partition P3 N state for x = 0 ext N state for x = 1 ext Partition P4 = P3

Partition blocks (ABCDE) 11100 00011 (ABC) (DE) CCB DE BEE BA (A) (BC) (DE) C CB DE B EE BA (A) (BC) (D) (E) C CB D E B EE B A (A) (BC) (D) (E) States B and C are equivalent

A ction Separate (ABC) and (DE) Separate (ABC) and (DE)

Separate (A) and (BC)

Separate (D) and (E)

Figure 9.3

Example 9.2 -- Partitioning example

x 0 A B C D E F G H E/0 A /1 C/0 B/0 D /1 C/0 H /1 C/1 (a) 1 D /0 F/0 A /1 A /0 C/0 D /1 G /1 B/1 A' C' D' E' x 0 B'/0 C'/0 E'/1 C'/1 B' A '/1 1 A '/0 C'/0 A '/1 D '/1 B'/1

(b)

Figure 9.4

Example 9.3 -- Another partitioning example

x 0 A B C D E F G H A /0 H /1 E/0 C/1 C/1 F/1 B/0 H /1 (a) 1 B/0 C/0 B/0 D /0 E/0 G /1 F/0 C/0 B' C' D' E' F' 0 A' A '/0 B'/1 F'/0 E'/0 E'/1 C'/1 x 1 E'/0 D '/1 E'/0 B'/0 C'/0 F'/0

(b)

Figure 9.5

Example 9.4 -- Yet another partitioning example

00 A B C D E F G H D /0 C/1 C/1 D /0 C/1 D /0 G /0 B/1 x1x2 01 11 D /0 D /0 D /0 B/0 F/0 D /0 G /0 D /0 (a) F/0 E/1 E/1 A /0 E/1 A /0 A /0 E/1 10 A /0 F/0 A /0 F/0 A /0 F/0 A /0 A /0 A' B' C' D' E' 00 C'/0 B'/1 C'/0 B'/1 E'/0 x1x2 01 11 C'/0 C'/0 B'/0 E'/0 10

A '/0 A '/0 D '/1 A '/0 A '/0 A '/0 A '/0 A '/0

A '/0 D '/1 A '/0

(b)

Figure 9.6

Finding Equivalent States by Implication Tables

x 0 A B C D E C/1 C/1 B/1 D/0 E/0 (a) 1 B/0 E/0 E/0 B/1 A/1 D E A B (b) B C D E A B (d) C AB D BE BC BE BE BC BE A B C D AB A B (e) C D (BC) C D D E A B (c) C D B C B C

B C D E

PK = (A)(BC)(D)(E) (f)

Figure 9.7

Example 9.5 -- Using implication tables to find equivalent states

x 0 A B C D E F G H E/0 A/1 C/0 B/0 D/1 C/0 H/1 C/1 (a) A B C D E F G (AD) (BE) (CF) 1 D/0 F/0 A/1 A/0 C/0 D/1 G/1 B/1 E F G H A B C D (b) E F CH BG G D BE AD CF AD B C

PK = (AD)(BE)(CF)(G)(H) (c)

Figure 9.8

Example 9.6 -- An implication table example

00 A B C D E F G H D/0 C/1 C/1 D/0 C/1 D/0 G/0 B/1 01 x1x2 11 10 A/0 F/0 A/0 F/0 A/0 F/0 A/0 A/0 E F G H A DG AF BC AF B BC C D (b) D B C BD AF DF DF AF BD BG AF BC DF E F G DG AF AF D/0 D/0 D/0 B/0 F/0 D/0 G/0 D/0 (a) A B C D E F G (AF) (BC)(BH) (CH) F/0 E/1 E/1 A/0 E/1 A/0 A/0 E/1

Note: (BC)(BH)(CH) = (BCH) PK = (AF)(BCH)(D)(E)(G) (c)

Incompletely Specified Circuits

Next states and/or outputs are not specified for all states Applicable input sequences: an input sequence is applicable to state, Si, of an incompletely specified circuit if and only if when the circuit is in state Si and the input sequence is applied, all next states are specified except for possible the last input of the sequence. Compatible states: two states Si and Sj are compatible if and only if for each input sequence applicable to both states the same output sequence will be produced when the outputs are specified. Compatible states: two states Si and Sj are compatible if and only if the following conditions are satisfied for any possible input Ip
The outputs produced by Si and Sj are the same, when both are specified The next states Sk and Sl are compatible, when both are specified.

Incompatible states: two states are said to be incompatible if they are not compatible.

Compatibility Relations
Compatibility relation: let R be a relation on a set S. R is a compatibility relation on S if and only if it is reflexive and symmetric. A compatibility relation on a set partitions the set into compatibility classes. They are typically not disjoint. Example: let S = {A,B,C,D,E} and R = {A,A),(B,B),(C,C),(D,D),(E,E),(A,B),(B,A),(A,C),(C,A), (A,D), (D,A),(A,E),(E,A),(B,D),(D,B),(C,D),(D,C),(C,E),(E,C)} Then the compatibility classes are (AB)(AC)(AD)(AE)(BD)(CD)(CE)(ABD)(ACD)(ACE) The incompatibility classes are (BC)(BE)(DE) Compatible pairs may be found using implication tables Maximal compatibles may be found using merger diagrams

Examples 9.8 and 9.9 -- Generating Maximal Compatibles and Incompatibles

G F E E D C C B A A A AC CD AD AC AC CG CH CD D (b) AG CG DG AG G F E D D C B B B A A (GH) (GH)(FG) (EG)(EH)(GH)(FG) (FG)(EGH) (DG)(FG)(EGH) (CG)(CF)(CE)(CD)(DG)(FG)(EGH) (CEG)(CDG)(CFG)(EGH) (BC)(BG)(CEG)(CDG)(CFG)(EGH) (AE)(AG)(AH)(BC)(BG)(CEG)(CDG)(CFG)(EGH) (AEG)(AGH)(AEH)(BCG)(CEG)(CDG)(CFG)(EGH) (AEGH)(BCG)(CDG)(CEG)(CFG) (c) (FH) (FH)(EF) (FH)(EF)(DH)(DF)(DE) (FH)(DH)(DEF) (CH)(FH)(DH)(DEF) (BH)(BF)(BE)(BD)(CH)(FH)(DH)(DEF) (BH)(BDEF)(CH)(FH)(DH) (BDEF)(CH)(BDFH) (AB)(AC)(AD)(AF)(BDEF)(CH)(BDFH) (ABDF)(AC)(BDEF)(CH)(BDFH) (d)

x 0 A B C D E F G H A/B/G/C/1 A/1 D/G/H/(a) 1 C/1 A/E/0 C/C/A/G/D/-

B C D E F G H

AC BG AE AC AD AC CG CD A BC AC AB AC BD AG AD B CG CE AG DG AE EG GH DE C

AH DH DG CD AD E F G

Merger diagrams
B B C

A (a) B

A (b) C B

A E (c) D F (d)

Figure 9.11

Example 9.10 -- Merger diagrams for example 9.8

B A

C D A

C D

H G (a) F

H G (b) F

Figure 9.12

Minimization Procedure
Select a set of compatibility classes so that the following conditions are satisfied
Completeness: all states of the original machine must be covered Consistency: the chosen set of compatibility classes must be closed Minimality: the smallest number of compatibility classes is used

Bounding the number of states

Let U be the upper bound on the number of states needed in the minimized circuit Then U = minimum (NSMC, NSOC)
where NSMC = the number of sets of maximal compatibles and NSOC = the number of states in the original circuit

Let L be the lower bound on the number of states needed in the minimized circuit Then L = maximum(NSMI1, NSMI2,, NSMIi)
where NSMIi = the number of states in the ith group of the set of maximal incompatibles of the original circuit.

State Reduction Algorithm

Step 1 -- find the maximal compatibles Step 2 -- find the maximal incompatibles Step 3 -- Find the upper and lower bounds on the number of states needed Step 4 -- Find a set of compatibility classes that is complete, consistent, and minimal Step 5 -- Produce the minimum state table

Example 9.11 -- Reduced state table corresponding to example 9.8

x 0 (BCG) (CDG) (CFG) (CEG) 1 A' B' D' E' 0 A'/1 B'/A'/1 C'/(b)
Figure 9.13

x 1 C'/1 A'/0 D'/0 A'/0

(AEGH) AGH CDG BG AEG CG CEG DG AEG AG CEG (a)

C' B', C', D', E'/1 D'/0

Example 9.12 -- State reduction problem

x 0 A B C D E A/C/1 D/0 -/A/0 (a) 1 -/B/0 -/1 B/C/1 C D E B AC AD A A B x 0 A C (ABD) (ACD) (ACE) E (d) D AC AD AD (e) 1 B B C A' B' 0 B'/1 A'/0 (f) x 1 A'/0 B'/1 B (b) AD C BC E D (c) D C B

Figure 9.14

Example 9.13 -- Another state table reduction problem

x 0 A B C D E F B/1 -/E/0 B/1 -/-/0 (a) C B D 0 B' A F (e) E C' D' C'/0 -/-/0 (f) 1 D/0 B/0 D/A/0 C/1 E/1 D E F A B (b) x 1 A'/0 B'/1 C'/1 A' A', B'/1 A'/0 C BD AB CD DE C D CE E A F (c) E B D (ABD) (BC) (E) (F) B BD C 0 B E (d) x 1 ABD BD C E

Figure 9.15

Example 9.14 -- Yet another state reduction problem

x 0 A B C D E D/E/0 D/0 C/C/1 (a) 1 A/A/B/C/B/E B C D DE AB AC CD AB CD A B (b) x 0 (ABC) (ACD) (ADE) DE CD CD (e) 1 AB ABC ABC 0 (ABC) DE (DE) C (f) C AB DE AC CE BC BC D E (c) D E (d) D A B B

x 1 AB BC A' B' 0 B'/0 A'/1

x 1 A'/A'/-

Figure 9.16

(g)

Example 9.15 -- Optimal state assignments

x Present 0 1 state A B/0 E/0 B C D E F G C/0 D/0 A/1 G/0 A/0 F/0 G/0 F/0 A/0 C/0 A/1 D/0

N state/output ext

Figure 9.17

Unique State Assignments for Four States

x Present 0 1 state A A/0 B/0 B C D A/0 C/0 C/1 (a) C/0 D/0 A/0

A ssignm ents 1 States A B C D

y1 y2

2
y1 y2

3
y1 y2

00 01 11 10

10 11 01 00 (b)

00 10 11 01

Figure 9.18

State Assignments for a Four State Machine

x 0 A B C D C/0 C/0 B/0 A /1 1 D /0 A /0 D /0 B/1

Figure 9.19

D flip-flop realization for assignment 1

y2y1 x 0 1 00 11/0 10/0 01 11/0 00/0 11 01/0 10/0 10 00/1 01/1 Y2 Y1/z (a) x y2 y1 00 01 11 y2 10 1 z (b) 1 0 0 0 0 x 1 0 0
y1

x y2 y1 00 01 11 y2 10 0 D2 (c) 0 1 1 0

x 1 1 0 y1 1 y2 0 y2 y1

x 0 00 01 11 10 1 1 1 0 D1 (d)

x 1 0 0 y1 0 1

Figure 9.20

D flip-flop realization for assignment 2

y2y1 x 0 1 00 01/0 10/0 01 11/0 10/0 11 01/0 00/0 10 00/1 11/1 Y2 Y1/z (a) x y2 y1 00 01 11 y2 10 1 z (b) 1 0 0 0 0 x 1 0 0 y1 0 y2 10 0 D2 (c) 1 11 0 0 y2 10 0 D1 (d) 1 y2 y1 00 01 x 0 0 1 x 1 1 1 y1 11 1 0 y2 y1 00 01 x 0 1 1 x 1 0 0 y1

Figure 9.21

D flip-flop realization for assignment 3

y2y1 x 0 1 00 01/0 11/0 01 10/0 11/0 11 00/1 10/1 10 01/0 00/0 Y2 Y1/z (a) x y2 y1 00 01 11 y2 10 0 z (b) 0 0 0 0 1 x 1 0 0 y1 1 y2 11 10 0 0 D2 (c) 1 0 y2 y1 00 01 x 0 0 1 x 1 1 1 y1 y2 11 10 0 1 D1 (d) 0 0 y2 y1 x 0 00 01 1 0 x 1 1 1 y1

Figure 9.22

State adjacencies for four-state assignments

y1 0 1

0 A B

y2

1 D C

y1 0 1

0 A C

y2

1 D B

y1 0 1

0 A C

y2

1 B D

(a)

(b)

(c)

Assignment 1

Assignment 2

Assignment 3

Figure 9.23

Example 9.18 -- Implication Graphs

x 0 A B C D B/0 D/0 A/1 D/1 (a) BD AB AC CD AD BC 1 C/0 A/1 D/0 B/1

(b)

Figure 9.24

Example 9.19 -- Closed subgraphs

x 0 A B C D E B/0 C/1 B/0 A/0 B/1 (a) BD AE AC 1 E/0 D/1 A/0 D/0 A/1 Closed subgraph CD AB BC AD DE

Closed subgraph (b)

Figure 9.24

Example 9.20 -- Optimal state assignment

y2y1 A C D B x 0 1 00 10/0 01/0 01 00/1 11/0 11 11/1 10/1 10 11/0 00/1 Y2 Y1/z (a) x y2y1 00 01 11 y2 10 1 D2 0 0 1 0 1 x 1 0 1 y1 1 y2 10 1 D1 (b) 0 11 1 0 y2 10 0 z 1 y2y1 00 01 x 0 0 0 x 1 1 1 y1 11 1 1 y2y1 x 0 00 01 0 1 x 1 0 0 y1

Figure 9.26

Example 9.21 -- Another state assignment problem

BE x 0 A B C D E E/0 A/1 E/0 A/0 D/0 (a) 1 B/0 D/1 A/0 B/1 C/0 Closed subgraph (b) y3 y2
0

CD

AB

AD

AE

BC AC

BD

DE

Closed subgraph CE

y3 00 A
2 3

y1

01 D

6 7

11 B

4 5

10 C

0 y1 1
1

E y2 (c)

Figure 9.27

A D flip-flop realization of the previous example

y3 y2 y1 x 0 1 y2 y1 xy3
0

x 00
4 5

01

12 13

11

8 9

10

A 000 001/0 110/0 B 110 000/1 010/1 C 100 001/0 000/0 D 010 000/0 110/1 E 001 010/0 100/0 Y3 Y2 Y1/z (a) y2

00
1

01
3 7

d
15

d
11

y1 d

11
2

d
6

d
14

d
10

10

1 y3 (b)

xy3 y2 y1 00
1 5 13 0

x 00
4

xy3 10 1 y2 y1 00
1 5 13 0

x 00
4

01

12

11

8 9

01

12

11

8 9

10 1

y2 y1

xy3
0

x 00 1
1 5 4

01 1

12 13

11

8 9

10

00 01

01
3 7

d
15

d
11

1 y1 d
10

01
3

1
7

d
15

d
11

d
3 7 15

d
11

y1 d 11 y2 1 10

y1 d

y2

11
2

d
6

d
14

11 y2
2

d
6

d
14

d
10

d
2 6

d
14

d
10

10 y3 (c)

10 y3 (d)

y3 (e)

Figure 9.28

Example 9.24 -- Closed partitions

x 0 A B C D E F D/0 E/0 F/1 A/1 C/0 B/0 (a) 1 C/0 A/1 B/0 F/1 E/0 D/1 (b) AB DE AC EF BC DF

Figure 9.29

Example 9.25 -- Cross dependency

0,1
B21 B32

Present block
P2: B21 B22 P3: B31 B32

Input 0 1
B32 B31 B21 B22 B32 B31 B21 B22

0,1
B22

0,1
B31

(a)
Figure 9.30

0,1 (b)