PLDs

Programmable Logic Devices (PLD)

General purpose chip for implementing circuits Can be customized using programmable switches

Main types of PLDs

PLA PAL ROM CPLD FPGA

PLD (Programmable Logic Device)

All layers already exist

Designers can purchase an IC Connections on the IC are either created or destroyed to implement desired functionality Field-Programmable Gate Array (FPGA) very popular Low NRE costs, almost instant IC availability Bigger, expensive (perhaps $30 per unit), power hungry, slower
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Benefits

Drawbacks

Vahid & Givargis

PLD as a Black Box

Inputs

(logic variables)

Logic gates and programmable switches

(logic functions)

Outputs

Programmable Logic Array (PLA)

x1 x2

xn

Use to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are programmable

Input buffers and inverters xn xn P1 AND plane OR plane

x1 x1

Pk

f1

fm

Comparison
Technology Performance/ Cost Time until running Time to high performance Time to change code functionality

ASIC

Very High Medium High

Very Long Very Long Medium Long Long Long Not Attainable

Impossible Medium Long Very Short

Speed

FPGA ASIP/ DSP Generic

Low-Medium Very Short

Flexibility

PLD Definition

Programmable Logic Device (PLD):

An integrated circuit chip that can be configured by end use to implement different digital hardware Also known as Field Programmable Logic Device (FPLD)

PLD Advantages

Nonrecurring engineering cost PLD

Short design time Less expensive at low volume

ASIC

Volume

PLD Categorization
PLD SPLD
Simple PLD

HCPLD
High Capacity PLD

Programmable Logic Array

PLA

PAL
Programmable Array Logic

CPLD
Complex PLD

FPGA
Field Programmable Gate Array
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Programmable ROM (PROM)

N input

xM ROM

M output

Address: N bits; Output word: M bits ROM contains 2

words of M bits each

The input bits decide the particular word that becomes available on output lines

Logic Diagram of 8x3 PROM

Sum of minterms
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Combinational Circuit Implementation using PROM

PROM Types

Programmable PROM

Break links through current pulses Write once, Read multiple times Program with ultraviolet light Write multiple times, Read multiple times

Erasable PROM (EPROM)

Electrically Erasable PROM (EEPROM)/ Flash Memory

Program with electrical signal Write multiple times, Read multiple times
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PROM: Advantages and Disadvantages

Widely used to implement functions with large number of inputs and outputs Design of control units (Micro-programmed control units) For combinational circuits with lots of dont care terms, PROM is a wastage of logic resources

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Programmable Logic Array

n x k links k AND gates n inputs n x k links m OR gates k X m links m outputs

Programmable AND array + programmable OR array n x k x m PLA has 2n x k + k x m links Sum of products
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PLA 4 X 6 X 2

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Logic Implementation with PLA

Finite number of AND gates => simplify function to minimum number of product terms Number of literals in a product term is not important since we have all the input variables Sharing of product terms between outputs => multiple-output minimization

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Design with PLA

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Programmable Array Logic (PAL)

Programmable AND array Fixed OR array

Each output line permanently connected to a specific set of product terms

Number of switching functions that can be implemented with PAL are more limited than PROM and PLA

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PAL Logic Diagram

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Design with PAL

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PAL Implications

Number of product terms per output > number of product terms in each sum-ofproduct expression No sharing of product terms between outputs

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Comparing PALs and PLAs

PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs PALs are simpler to manufacture, cheaper, and faster (better performance) PALs also often have extra circuitry connected to the output of each OR gate

The OR gate plus this circuitry is called a macrocell

Macrocell

Select
0 1

Enable f1

OR gate from PAL

D Clock

Flip-flop

back to AND plane

CPLD

I/O Logic Block

Programmable Interconnect

Logic Block

Logic Block I/O Logic Block

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CPLD Logic Block

Simple PLD

Inputs Product-term array Product term allocation function Macro-cells (registers)

Logic blocks executes sum-of-product expressions and stores the results in micro-cell registers Programmable interconnects route signals to and from logic blocks

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Major CPLD Resources

Number of macro-cells per logic block Number of inputs from programmable interconnect to logic block Number of product terms in logic block

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Structure of FPGA (Xilinx)

Logic Block

I/O Block

Interconnect

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Logic Function

Implemented as look-up table (LUT) K-input LUT corresponds to 2 x 1 bit memory K-input LUT can implement any k-input 1output logic function
K

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Configuring FPGA

Configure CLB and IOB Configure interconnect Interconnect technology

SRAM Anti-fuse (program once) EPROM / EEPROM

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Programming Technology
Name EPROM EEPROM SRAM Antifuse Re-programmable yes (out of circuit) yes (in circuit) yes (in circuit) no Volatile no no yes no

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FPGA Applications

Glue Logic (replace SSI and MSI parts) Rapid turnaround Prototype design Emulation Custom computing Dynamic reconfiguration

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PLD Logic Capacity

SPLD: about 200 gates CPLD

Altera FLEX (250K logic gates) Xilinx XC9500 Xilinx Vertex-E ( 3 million logic gates) Xilinx Spartan (10K logic gates) Altera

FPGA

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FPGA Design Flow

Design Entry

Design Implementation

Design Verification

FPGA Configuration

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Design Entry (DK1 in our case)

Schematic Compile

HDL

Logic Equations Minimize Reduced Logic Equations (Netlist)

Test vectors

Simulation
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CPLD

Complex Programmable Logic Devices (CPLD) SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms

Combined number of inputs + outputs < 32 or so

CPLDs contain multiple circuit blocks on a single chip

Each block is like a PAL: PAL-like block Connections are provided between PAL-like blocks via an interconnection network that is programmable

Structure of a CPLD
I/O block

I/O block

PAL-like block

PAL-like block

Interconnection wires

I/O block

I/O block

PAL-like block

PAL-like block

Internal Structure of a PAL-like Block

Includes macrocells

PAL-like block

Usually about 16 each

Fixed OR planes

OR gates have fan-in between 5-20

DQ

XOR gates provide negation ability

DQ

XOR has a control input

More on PAL-like Blocks

CPLD pins are provided to control XOR, MUX, and tri-state gates When tri-state gate is disabled, the corresponding output pin can be used as an input pin

The associated PAL-like block is then useless

The AND plane and interconnection network are programmable Commercial CPLDs have between 2-100 PAL-like blocks

Programming a CPLD

CPLDs have many pins large ones have > 200

Removal of CPLD from a PCB is difficult without breaking the pins Use ISP (in system programming) to program the CPLD JTAG (Joint Test Action Group) port used to connect the CPLD to a computer

Example CPLD
(from inte rconne ction wire s)
x1 x2

Use a CPLD to implement the function

unuse d

PAL-like block 0 0
D Q

1 f

FPGA

SPLDs and CPLDs are relatively small and useful for simple logic devices

Up to about 20000 gates

Field Programmable Gate Arrays (FPGA) can handle larger circuits

No AND/OR planes Provide logic blocks, I/O blocks, and interconnection wires and switches Logic blocks provide functionality

I/O block Structure of an FPGA

interconnection switch

I/O block

logic block

I/O block

I/O block

LUTs

Logic blocks are implemented using a lookup table (LUT)

Small number of inputs, one output Contains storage cells that can be loaded with the x1 desired values
0/1

A 2 input LUT uses 3 MUXes to implement any desired function of 2 variables

0/1 0/1 0/1

Shannon's expansion at work!

x2

x1 0 0 1 1

x f Example 2 Input LUT

0 1 0 1

1 0 0 1

f = x1'x2' + x1x2, or using Shannon's expansion: f = x1'(x2') + x1(x2) = x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))

x1 1 0 0 1 x2 f

3 Input LUT

x1 x2 0/1 0/1 0/1 0/1 f

7 2x1 MUXes and 8 storage cells are required

Commercial LUTs have 0/1 4-5 inputs, and 16-32 0/1 storage cells 0/1
0/1 x3

Programming an FPGA

ISP method is used LUTs contain volatile storage cells

None of the other PLD technologies are volatile FPGA storage cells are loaded via a PROM when power is first applied

The UP2 Education Board by Altera contains a JTAG port, a MAX 7000 CPLD, and a FLEX 10K FPGA

The MAX 7000 CPLD chip is EPM7128SLC84-7

Example FPGA
x3 f

Use an FPGA with 2 input LUTS to implement the function f = x1x2 + x2'x3 x
1

f1 = x1x2 f2 = x2'x3 f = f1 + f2

x2

x1 0 0 0 x2 1

f1

x2 0 1 0 x3 0

f2

f1 0 1 1 f2 1

Another Example FPGA

Use an FPGA with 2 input LUTS to implement the function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

Fan-in of expression is too large for FPGA (this was simple to do in a CPLD) Factor f to get sub-expressions with max fan-in = 2

f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5) = (x1x6' + x2x7)(x3 + x4x5)

Could use Shannon's expansion instead

FPGA Implementation x x
4 5

x3

x1

f = (x1x6' + x2x7)(x3 + x4x5)

x6

x2 x2 0 0 B x7 0 1 A 0 1 D 1 B 1 D 0 0 f 0 E 1

x7

Standard Cells

Rows of logic gates can be connected by wires in the routing channels

Designers (via CAD tools) select prefab gates from a library and place them in rows Interconnections are made by wires in routing channels

x1 x2 x3

Multiple layers may be used to avoid short circuiting A hard-wired connection between layers is called a via f
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f1

Example: Standard Cells

f1 = x1x2 + x1'x2'x3 + x1x3' f2 = x1x2 + x1'x2'x3 + x1x3

x1 x2 x3

f1

Sea of Gates Gate Array

A Sea of Gates gate array is just like a standard cell except all gates are of the same type

Interconnections are run in channels and use multiple layers Cheaper to manufacture due to regularity

Example: Sea of Gates

black bottom layer channels

f1 = x2x3' + x1x3

red top layer channels

Digital Logic Technology Tradeoffs

Speed / Density / Complexity / Likely Market Volume

Engineering cost / Time to develop