INTRODUCTION TO Digital Design Using HDL (Hardware Descriptive Language.

)
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How to tackle a 'million-gates' design?

Need good methodologies to handle the
complexity o Top-down Design approach Hierarchy, Modularity, Design reuse o Higher level of abstraction o Integrated design and verification

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How to tackle a 'million-gates' design?

De-emphasis of hand design methods - use
EDA tools o Behavioural Synthesis, Logic synthesis o Software prototyping Software simulator replaces the breadboard o Hardware design begins to carry out like software

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How to tackle a 'million-gates' design?

Digital logic design is a 'a day to learn, a lifetime
to master'. Technology: o SSI MSI LSI VLSI ULSI You can utilize different types of implementation technology (e.g. ASIC, Programmable Logic Device) with provision up to few 'million' gates. o What challenges are faced by modern digital designers? o How do you tackle such a 'million-gates' design?
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How to tackle a 'million-gates' design?

In the digital design community, the term RTL
design is commonly used for a combination of dataflow modeling and behavioural modeling. Modern definition of a RTL code o any code that is synthesizable is called RTL code.

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DSP(Digital Signal Processing Card)

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INTRODUCTION
Design Ideas

Behavioral Design
Flow Chart, Pseudo Code,

Data Path Design

Bus & Register Structure

Logic Design
Gate Wirelist, Netlist

Physical Design
Transistor List, Layout,..

Manufacturing Chip or Board

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Emergence of HDLs - What is a HDL?

A high-level programming language offering
special constructs to model microelectronic circuits o Describe the operation of a circuit at various levels of abstraction Behaviour Function Structure o Describe the timing characteristics of a circuit o Express the concurrency of circuit operation
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Why Use the HDLs?

NO OTHER CHOICE (Why?) it is very difficult to design directly on transistoror gate-level hardware o for complex system, gate-level design is dead mixed-level modeling and simulation easier to explore different design options reduce time and cost

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HDL(Hardware Description Language)

Characteristics of digital hardware Connections of parts

Concurrent operations
Concept of propagation delay and timing Characteristics cannot be captured by traditional PLs Require new language: HDL

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Specify

Capture

Verify

Formalize

Implement

Main Design Phases in a Development Cycle

HDL supports Specify (for design specification) Capture (for design entry) Verify (for design simulation) Formalize (for documentation) Implement (for logic synthesis)
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Advantages of HDLs
advantages compared to traditional schematicbased design o design with RTL description + logic synthesis tools different levels of abstraction easier and cheaper to explore different design options with the aid of a logic synthesis tool HDL offers the mechanism to describe, test and synthesize such complex design design reuse
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Advantages of HDLs
o

functional verification can be done early optimized to meet the desired functionality analogous to computer programming textual description and comments

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Design Entry

Test Development

Synthesis

Functional Simulation

Device Fitting/Mapping

Timing Simulation

Device

HDLs can be used for both d e s i g n e nt ry a n d te s t development . HDL makes it easy to build, use and r euse lib raries of circuit elements.

2 Main Roles of a HDL in Digital Design

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Two HDLs Used Today

VHDL and Verilog Syntax and appearance of the two language are very different Capabilities and scopes are quite similar Both are industrial standards and are supported by most software tools

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VHDL Vs Verilog HDL

VHDL
open standard (originated by USA DoD) oriented to system-level design or specification probably better for design verification tasks, but less technology support for ASIC implementation complex syntax and abstract steep learning curve demanding good programming background Good but too demanding for new learners, like you

Verilog
open standard (initiated by OVI) oriented to digital circuit design well support from EDA and ASIC vendors C-like syntax and more intuitive students should have some prior programming experience on C shallow learning curve than VHDL Future compatibility to Digital IC Design modules

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Genesis of VHDL
VHDL is a language for describing digital hardware used by industry worldwide

Multiple design entry methods and hardware description languages in use

No or limited portability of designs between CAD tools from different vendors Objective: shortening the time from a design concept to implementation from 18 months to 6 months

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What is VHDL?
VHDL is the VHSIC ( Very High Speed Integrated Circuit ) Hardware Descriptive Language.
A Simulation Modeling Language.

A Design Entity Language.

A standard Language. A Netlist Language.

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How is VHDL used?

For Design specification. For Design capture. For Design simulation. For Design documentation.
As an alternative to schematics.
As an alternative to proprietary languages.
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Features of VHDL
Support for concurrent statements ( All elements are active simultaneously).
Library support (user defined and system predefined ). Sequential statements (gives software-like sequential control (e.g. case, ifthen-else, loop, ). Support for design hierarchy.
Generic design (configurable for size, physicsl characteristics, timing, loading,). Use of subprograms. Type declaration and usage. - Not limited to Bit or Boolean types - Allow integers, floating point types, as well as user defined types. - Possibility to define new operators for the new types ). Timing control. Technology independent.
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System Algorithmic { Behaviour RTL { { Data Flow Gate Switch

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Different Levels of Abstraction of a Typical Digital System

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Levels of Abstraction
Two basic ways of representing a digital circuit
o

Structure primitives and connectivity tools: schematic diagram Behaviour I/O functions vs time tools : Equations, Timing Waveforms, HDL

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Abstraction Level Switch

Structure transistors, resistors, capacitors, gates, latches, flip-flops adders, comparators, multiplexers, registers, counters, queues, datapaths, memories CPU, memories, buses, ASICs

Behaviour I-V diagrams, differential equations Boolean equations, truth tables, state diagrams, timing diagrams flowcharts, algorihtms, generailized FSMs executable specifications, programs

Gate

Register

Processor

Structural and Behavioural Representation at Different Levels of Abstraction

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Levels of Abstraction
Physical/Switch/Transistor Level
a model that describes layout of the wires, resistors, capacitors and transistors and interconnections between them on an IC chip Gate-level o a circuit is described in terms of logic primitives (such as AND, OR, XOR, NAND, NOR, .), flip-flops, interconnections, logic levels and timing properties (e.g. gate delay)
o

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Levels of Abstraction
Register Transfer Level (Dataflow)
o

a type of behavioural description that describes the flow of data between registers and how a design processes these data defines signal values with respect to a clock RTL (Register Transfer Level) is frequently used for the Verilog description with the combination of behavioural and dataflow constructs which is acceptable to logic synthesis tools
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Levels of Abstraction
Behavioural Modeling
o o

highest level of abstraction a component is described by its design algorithms and/or input/output responses without implying any hardware details of implementation behaviour is implied by the functional definitions of the components synthesis tools accept only a limited subset of these high-level constructs
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Black Box F

Behaviour
D Q Logic D Q

RTL A B C D

CLK

CLK

Gate

Layout

Different Levels of Abstraction

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Automation Tools fast less simulation precise Humanoriented

Information Contents Functional timing behaviour e.g. "after 10ns, signal A switches to 1" Describe clock, dataflow, functions and events

Behaviour Behavioural Synthesis RTL Logic Synthesis

Machineoriented

Logic Placement & Routing Layout

Gate types, connections and gate delays Shape, dimensions, path delays

more slow simulation precise

Tools and Information Contents for Different Levels of Abstraction

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Digital Design Flow

Essential steps:
o o o o

o
o

Design Entry RTL Simulation Logic Synthesis Verification Placement and Routing Configuration

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Design Entry

Technology-independent
RTL HDL Design Constraints

Test Bench

Functional Simulation

Technology Library

Logic Synthesis

Technology-dependent
Gate-level Netlist

Test Bench

Post-synthesis Simulation

Fitting / Place & Route

Layout Data

Timing Extraction

Modern Digital Design Flow

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Test Bench

Post-layout SImulation

Simulation Library

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Design Entry
Schematic Diagram Text-based Entry e.g. ABEL, Verilog, VHDL

Functional Simulation

Design Verification
Functional and Timing Simulation Static Timing Analysis In-circuit Verification

Back-annotation

Design Implementation
Optimization FPGA - Mapping, Placement, Routing CPLD - Fitting Bit Stream Generation

Download to a Target PLD Device

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Digital Design Flow (with a PLD as target)

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Synthesis
Translation of a high-level design to a lowerlevel form o Map a more abstract representation to an optimized and more physical form
IP Blocks VHDL or Verilog Behavioural Synthesis Register Transfer Design Data Files Other EDA Tools

Logic Synthesis

Gate-level Netlists or Schematics

VHDL or Verilog

Technology Libraries

Synthesis Tools Used in Modern Digital design

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Synthesis
Logic Synthesis the predominate synthesis
technology in use today o a design is specified at the RTL level o capable of optimizing a design with respect to various constraints, such as area, timing, power o an optimized gate-level implementation that is targeted to a particular technology o requiring a technology library to specify the components to be used in the design
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HDL Description always @(state) begin hwy = GREEN; cntry = RED; if (clear) Q <= 4'd0; else Q <= Q + 1; end

Technology-independent

Logic Synthesis Tools Design Constraints Technology Libraries IP Cores Reports all constraints met ?

Are a Timing Powe r Constraints Constraints Constraints

Other constraints, e.g. Testability Gate-level Netlist ( Optimized ) A SEL B s _ y x F Technology-dependent

The Logic Synthesis Process

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Synthesis
Behavioural synthesis
an emerging technology that allows a more algorithmic specification of the system to be synthesized exploring design alternativesConsideration to be taken when carrying out a HDL-based design for logic synthesis: o synthesizable subset o synthesis policy o modeling style o functionally identical vs functionally equivalent
o
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Circuit Description module FA (SUM, CO, A, B CIN) output SUM, COUT, input A, B, CIN; ... ... endmodule

Testfixture module testFixture; reg A, B; ... ... ... endmodule

Verilog Simulator
Verilog Parser

User Interface

Simulator Engine

Graphical Simulation Results

Text Mode Simulation Results

The Verilog Simulation

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Developmental History of Verilog HDL

The future 1995 1991 1990 1989 1985 1980's
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Analog Verilog ?

Publication of IEEE Standard 1364

All rights transferred for Verilog HDL to OVI

Verilog HDL placed in the public domain (Why ?)

Cadence acquired Gateway and its Verilog-XL

Gateway Design Automation introduced Verilog-XL Simulator and its proprietory HDL

There were numerous proprieory HDLs in the academic and industrial sectors
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What is Verilog HDL ?

Hardware Description Language Mixed level modeling
Behavioural Dataflow Structural Switch Single language for design and simulation Concurrency Built-in primitives and logic functions User-defined primitives Built-in data types High-level programming constructs
o
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What is Verilog HDL ?

System

Programming Language Interface Algorithmic Hierarchial structure and instantiation Verilog modeling range
o

{ Behaviour From switch/transistor to RTL { processor level { Data Flow Our main focus will be on RTL

(Register Transfer Level)

Gate Switch
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General Design Process

Understand problem and generate block

diagram of solution Code block diagram in Verilog HDL Create verification script to test design Synthesize Verilog Run static timing tool to check all thing is met Design is mapped, placed and routed Bitstream (*.bit) file is generated and downloaded to target devices (e.g. FPGA or CPLD)
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Digital Design Technologies

Digital Design Methodologies

Full Custom IC

Semi Custom IC

Standard Cell

Gate Array

Field Programmable Logic

Digital Design Technologies

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Field Programmable Gate Array (FPGA)

Simple/Complex PLD (S/CPLD)

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Ease of Use Full-custom ICs Standard Cells FPGAs, Gate Arrays

* Market Volume to Amortize * Time to Prototype

PLDs

* Nonrecurring engineering cost * Design Complexity * Process complexity Characteristics of various * Logic Density * Speed Digital Design Technologies
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100,000

No. of Logic Gates / Chip

10,000 1,000 100 10

FPGA

Gate Array/Std.Cell ASICs

PLD

10

100 1,000

Design Cycle / Man-Days

Logic Density vs Design Cycle

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Total Cost

PLDS Gate Arrays

Fixed Cost Breakeven Qty Volume

Cost Comparison of PLDs and Gate Arrays

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Discrete Gates and Standard ICs cheap unit cost low levels of integration standard but limited functionality variety of stock required low performance Programmable Logic Devices (FPGAs, CPLDs)

Cell-based and Full-custom ASICs advanced and specialized functionality high level of integration high performance tailored for small market segment => inventory risk high non-recurring engineering cost high investment cost to cater for small-volume requirements

Comparison of Discrete Gates/Standard ICs and ASICs

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Classification
Programmable Logic Device (PLD) or Field
Programmable Logic Device (FPLD) o a generic term that refers to any integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs o fixed architecture but functionality programmable for a specific application

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PROM

PROMs are not classified as PLDs since they are mainly used for storage and special-purpose applications.

PLA, PAL SPLD

CPLD

FPGA

The Evolution of the PLD Technology

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 3 categories of PLDs: 1. SPLD (Simple Programmable Logic Device) PLA (Programmable Logic Array) PAL (Programmable Array Logic) Registered PAL 2. CPLD (Complex Programmable Logic Device) 3. FPGA (Field Programmable Gate Array)

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 3 basic characteristics distinguish PLDs from each other : o architecture of basic functional units o programmable interconnections o programming technology

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Architecture of PLDs
in[0] in[1] : : in[n-1] n inputs nxp AND Array (Programmable) P[0] P[1] : : P[p-1] pxm OR Array (Programmable) out[0] out[1] : : out[p-1] m outputs

p product terms fromed from inputs

Generic Architecture of PLDs

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 PLA o Two programmable planes: AND & OR planes o Any combinations of ANDs / ORs o Sharing of AND terms across multiple ORs o High logic density o High fuse count o Slower than PALs o Higher power dissipation than PALs

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Inputs Programmable OR Plane

Programmable AND Plane Programmable Element (e.g. Metallic Fuse, UV EPROM Cell) Outputs

The PLA Architecture

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 PAL o Programmable AND plane / Fixed OR plane o Finite combination of ANDs / ORs o Medium logic density o Low fuse count o Faster than PLAs

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Inputs

Fixed OR Plane

Programmable AND Plane

Programmable Element (e.g. Metallic Fuse, UV EPROM Cell)

The PAL Architecture

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Outputs

Inputs Fixed OR Plane D or T Flip-flops D CLK Q

Programmable AND Plane

D CLK

Clock

The Registered PAL Architecture

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 CPLD o Each basic logic block is constructed from registered PLDs o Central, global interconnects o Simple and deterministic timing o Easily routed o PLD tools add only interconnects o Wide, fast complex gating o Clock speed > 300MHz

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PLD

PLD

PLD

Programmable Interconnect

PLD

PLD

PLD

The CPLD Architecture

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Clock Inputs Dedicated Inputs Logic Array

Product Term Sharing Array

Output Logic Macrocells * Registers

Outputs

Basic PLD Block of a CPLD

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 FPGA o a regular structure of configurable logic blocks (or modules) and interconnects o Channel-based routing o Fine-grained configurable logic block o Post-layout timing analysis required o Tools more complex than CPLDs o Fast register pipelining

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Row 1

Horizontal Channel

Vertical Channel

Channel Channel

Row 2

Row 3

I/O Pads

Channel

Row 4

Configurable Logic Blocks (a) Matrix-based Architecture (e.g. Xilinx and QuickLogic devices)

Configurable Logic Blocks (b) Row-based Architecture (e.g. Actel devices)

The FPGA Architecture

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Interconnect Delay

Block Delay

Size of Logic Block

Both Interconnect Delay and Block Delay are dependent on the FPGA architecture
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 FPGA o 2 basic types of FPGAs: o Reprogrammable (SRAM-based)

o
o
o

SRAM determines interconnects SRAM defines logic in Look Up Table

Interconnect is anti-fuse Logic is traditional gates
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OTP (One-time Programmable)

o o

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Example:
Show how the PLD shown in the Figure can be used to implement typical 2-input logic functions: AND, OR, NAND, NOR, XOR and XNOR.

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Uses of Programmable Logic Devices

3 main uses of PLDs:
o o o

Replacement of glue logic (random logic) Implementing dedicated controller circuits Implementing finite state machines (FSM)

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Selection Criteria
Main factors to be considered when choosing a
PLD: o Process technology o Programming technology reprogrammable vs OTP UV EPROM, E2EPROM, RAM and Flash o Logic capacity Dont miss the hidden factor: utilization It is a surprise if you can achieve a utilization well over 70%.

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o o

o
o o

Dedicated logic functions E.g. Flip-flop types, I/O buffers, macrocells Timing characteristics & speed requirements Tpd, Tsetup, Thold, . Power dissipation Voltage requirements E.g. 2.5V, 3.3V, 5V I/O pins available Packages Special features E.g. In-system Programmability/Testability CAD tools and vendor-supplied libraries
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PLD Design Flow & Tools

Design Capture - schematics - HDL-based file

Synthesis

Functional SImulation

Device Fitting

Timing Simulation

Device Programming/ Downloading

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In-circuit Testing

Typical PLD Design Flow

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PLD Design Flow and Tools

CAD Tools are crucial to implementing digital
circuits in PLDs. PLD vendors usually offer series of free or lowcost CAD tools for users. o Examples: ISE Webpack from Xilinx MAX Plus from Altera ispLEVER from Lattice Semiconductor Warp from Cypress

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Idea
Sche matics ECS State M achine State CAD

HDL

Design Entry

Synthesis
Xilinx Synthe sis Te chnology (XST)

Translate
NGDBuild

CPLD Fitting
CPLD Fitte r

FPGA Mapping
M AP/PAR

Estimation
XPowe r

Programming
IM PACT Programme r

TestBench
HDL Be nche r

Simulate
M ode lSim XE

The Xilinx ISE Design Environment

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Example:
A sequential circuit is implemented into a PLD as in the following figure

(a) Identify the architecture of the PLD device.

i) architectural type

ii) no. of inputs

iii) no. of outputs iv) maximum number of product terms available for each output (b) Write a logic equation for each output.
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R' R S R S' S Q2' Q2 Q1' Q1

D CLK

Q Q Q Q Q Q

Q1

D CLK

Q2

D CLK

Q3

O4 O5 CLOCK

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Sample Design Process

*Problem:
Design a single bit half adder with carry & enable.

*Specification:
- Passes results only on enable high. - Passes zero on enable low.

- Result get x plus y .

- Carry gets any carry of x plus y .

x y enable

Half Adder

carry result

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Behavioral Design
Starting with algorithm, a high level description of the adder is created. IF enable=1 THEN result = x XOR y carry = x AND y ELSE carry = 0 result = 0

x y enable

Half Adder

carry result

*The model can now be simulated at this high level description to verify correct under standing of the problem.
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Data Flow Design

With the high level description confirmed, logic equations describing the data flow are then created.

carry = (x AND y) AND enable result = (xy OR xy ) AND enable

x y enable

(x AND y) AND enable (xy OR xy ) AND enable

carry result

*Again, the model can be simulated at this level to confirm the logic equations
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Logic Design
Finally, the structural description is created at the gate level

x y enable

carry result

*These gates can be pulled from a library of parts

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o o o

USA DoD:United States Department of Defense RTL:register-transfer level EDA or ECAD:Electronic design automation is a category of software tools for .... Logic simulation digital-simulation of an RTL or gate-netlist's digital (boolean ...

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