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Memory Interfacing

The document discusses the design and operation of computer memory. It explains that memory stores data and instructions and can be classified as main memory (RAM and ROM) or storage memory (disks, CDs, etc.). It describes how a microprocessor accesses information in memory using an address and data bus. It also discusses tri-state buffers, the basic memory element which is similar to a D latch, and how multiple memory chips are interfaced using address decoding and chip selects.

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252 views

Memory Interfacing

The document discusses the design and operation of computer memory. It explains that memory stores data and instructions and can be classified as main memory (RAM and ROM) or storage memory (disks, CDs, etc.). It describes how a microprocessor accesses information in memory using an address and data bus. It also discusses tri-state buffers, the basic memory element which is similar to a D latch, and how multiple memory chips are interfaced using address decoding and chip selects.

Uploaded by

nskvnr
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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The Design and Operation of Memory

Memory in a microprocessor system is where information (data and instructions) is kept. It can be classified into two main types:
Main memory (RAM and ROM) Storage memory (Disks , CD ROMs, etc.)

The simple view of RAM is that it is made up of registers that are made up of flip-flops (or memory elements).
The number of flip-flops in a memory register determines the size of the memory word.

ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information.
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Accessing Information in Memory

For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do the following:
Select the right memory chip (using part of the address bus). Identify the memory location (using the rest of the address bus). Access the data (using the data bus).

Tri-State Buffers

An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states:
Logic 0, logic1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely.

The Output is Low The Output is High

High Impedance 4

The Tri-State Buffer

This circuit has two inputs and one output.


The first input behaves like the normal input for the circuit. The second input is an enable.
If it is set high, the output follows the proper circuit behavior. If it is set low, the output looks like a wire connected to nothing.

Input

Outp ut Enabl e

OR

Input

Outp ut Enabl e
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The Basic Memory Element

The basic memory element is similar to a D latch. This latch has an input where the data comes in. It has an enable input and an output on which data comes out.
Data Input Data Output

Enable

EN

The Basic Memory Element

However, this is not safe.


Data is always present on the input and the output is always set to the contents of the latch. To avoid this, tri-state buffers are added at the input and output of the latch.
Data Input WR Enable EN D Q RD Data Output

The Design of a Memory Chip

Since we have tri-state buffers on both the inputs and outputs of the flip flops, we can actually use one set of pins only.
The chip would now look like this:

W R A1 A0

Input Buffers

RD

A d d r e s s

D e c o d e r

Memory Reg. 0
Memory Reg. 1 Memory Reg. 2 Memory Reg. 3 Output Buffers

D0 D1 D2 D3 RD W R A1 A0

D0 D1 D2 D3

Dimensions of Memory

Memory is usually measured by two numbers: its length and its width (Length X Width).
The length is the total number of locations. The width is the number of bits in each location.

The length (total number of locations) is a function of the number of address lines.
# of memory locations = 2( # of address lines) So, a memory chip with 10 address lines would have 210 = 1024 locations (1K) Looking at it from the other side, a memory chip with 4K locations would need Log2 4096=12 address lines
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Memory Map and Addresses

The memory map is a picture representation of the address range and shows where the different memory chips are located within the address range.
0000 0000

EPROM
3FFF 4400

Address Range of EPROM Chip

RAM 1

Address Range of 1st RAM Chip


5FFF 6000

Address Range

RAM 2 RAM 3
8FFF 9000 A3FF A400

Address Range of 2nd RAM Chip

Address Range of 3rd RAM Chip

RAM 4
F7FF FFFF

Address Range of 4th RAM Chip

1 0

Address Range of a Memory Chip

The address range of a particular chip is the list of all addresses that are mapped to the chip.
An example for the address range and its relationship to the memory chips would be the Post Office Boxes in the post office.
Each box has its unique number that is assigned sequentially. (memory locations) The boxes are grouped into groups. (memory chips) The first box in a group has the number immediately after the last box in the previous group.

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The steps of writing into Memory

What happens when the programmer issues the STA instruction?


The microprocessor would turn on the WR control (WR = 0) and turn off the RD control (RD = 1). The address is applied to the address decoder which generates a single Enable signal to turn on only one of the memory registers. The data is then applied on the data lines and it is stored into the enabled register.

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The 8085 and Memory

The 8085 has 16 address lines. That means it can address 216 = 64K memory locations.
Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc.

how would we use these address lines to control the multiple chips?

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The 8085 and Address Ranges

Now, we can break up the 16-bit address of the 8085 into two pieces: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Chip Selection Location Selection within the Chip

Depending on the combination on the address lines A15 - A10 , the address range of the specified chip is determined.

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Chip Select

Usually, each memory chip has a CS (Chip Select) input. The chip will only work if an active signal is applied on that input. To allow the use of multiple chips in the make up of memory, we need to use a number of the address lines for the purpose of chip selection.
These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used.

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Chip Select Example

A chip that uses the combination A15 - A10 = 001000 would have addresses that range from 2000H to 23FFH.
Keep in mind that the 10 address lines on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input:
A 10 A 11 A 12 A 13 A 14 A 15 CS

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Interface an IC 2764 with the 8085 using NAND gate address decoder such that the address range allocated to the chip is 0000H 1FFFH

Fig. 6.2 Pi Diagram of IC 2764

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Interface a 27128 EPROM (16K 8 bits or 16 KB) IC with the 8085 using a NAND gate address decoder such that the starting address assigned to the chip is C000H

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2 0

2 1

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