University of Kashan Department of Computer Engineering

MicroProcessors & MicroControlers

H. Sabaghian B. Spring 2006

hsabaghianb @ kashanu.ac.ir

Microprocessors

Text Books
Microcontroller 8051 Author: Mohammad ali Mazidi Translator: Dr. Sepidnam

The 8051 Microcontroller Author: Iscott Makenzi Translator: Dr. Seyed Razi Edition : 3

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Microprocessors

Introduction
Lec note 1

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Microprocessors

outline
Microprocessor Micro-computer Microcontroller 3_Bus (Data, Address, Control) I/O Memory

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Microprocessors

Microprocessor (P)(MPU)
P = CPU on a single chip Components of CPU
Registers: Temporary storage locations for program instruction or data. The Arithmetic Logic unit (ALU): performs both arithmetic and logical operations Timing and Control Circuits: keeps all working

together in the right time sequence

Bus: n_bit (internal) path for data exchange

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Microprocessors

Microprocessor
Microprocessor=P=MPU Tasks
processing data controlling all components make P the Computer system

P executes instructions in memory

Fetch, Decode, Execute

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Microprocessors

Microcomputers
Micro-computer (-Computer) small computer specifically for data acquisition and control applications

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Microprocessors

Microcomputers
All Microcomputers consist of (at least) :
Microprocessor Unit (P) Program Memory (ROM) Data Memory (RAM) Input / Output ports (IO) Bus System (External) (and Software)

MPU is the brain of microcomputer

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Microprocessors

The Input/Output (I/O) System

I/O links MPU to outside world. Input port : a circuit through which an external device can send signals (data?) to the MPU. Output port is a circuit that allows the MPU to send signals (data?) to external devices. I/O ports connect both digital and analogue devices by DAC and ADC

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Microprocessors

Bus
A common communications pathway that carry information between the various elements of system The term BUS refers to
a group of wires or conduction tracks on a printed circuit board (PCB)

though which binary information is transferred Subsystems are connected through BUS together

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Microprocessors

3_Bus
There are three main bus grouPs
ADDRESS BUS DATA BUS CONTROL BUS

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Microprocessors

Data Bus
The Data Bus carries the data which is transferred throughout the system. ( bi-directional) Examples of data transfers
Program instructions being read from memory into MPU. Data being sent from MPU to I/O port Data being read from I/O port going to MPU Results from MPU sent to Memory

These are called read and write operations

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Microprocessors

Address Bus
Address = binary number that identifies a specific memory storage location or I/O port involved in a data transfer

Address Bus = pathway transmit address to memory or I/O port. Address Bus is unidirectional (one way): addresses are always issued by the MPU
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Control Bus
Control Bus = grouP of control signals Control signals are unidirectional, and are mainly outputs from the MPU. provide synchronization (timing control) between MPU and other components. Example
RD: (read signal) read data into MPU WR: (write signal) write data from MPU
Microprocessors

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Main memory
Memory
Stores programs Provides data to the MPU Accepts result from the MPU for storage

Main memory Types

ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values
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Read-Only Memory
P can read instructions from ROM quickly Cannot write new data to the ROM ROM remembers the data, even after power cycled When power is turned on, the microprocessor will start fetching instructions from ROM (bootstrap )

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Microprocessors

Available ROMs
Masked ROM or just ROM PROM or programmable ROM(once only) EPROM (erasable via ultraviolet light) =UVROM Flash
re-writable about 10000 times usually must write a whole block not just 1 or 2 bytes, slow writing fast reading

EEPROM (electrically erasable ROM)

fast writing slow reading can program millions of times useless for storing a program good for save configuration information.
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ROM
m+1 bit Address

A0 A1 A2 Am

D0 D1 D2

Capacity :

m 1

2m1 (n 1)
ROM PROM EEPROM

n+1 bit Data

Dn

OE : Output Enable
CE (CS )

connect to RD of P : Chip Enable to Address decoder

CE

OE

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Microprocessors

ROM Read Timing

A0-Am

D0-Dn

CE

OE
OE falls to data valid Addr valid to data valid

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Microprocessors

27XX EPROM
U3 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE PGM CE VPP O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19
U1 8 7 6 5 4 3 2 1 23 22 19 20 18 21 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE CE VPP O0 O1 O2 O3 O4 O5 O6 O7 9 10 11 13 14 15 16 17

U2 8 7 6 5 4 3 2 1 23 22 19 21 20 18 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 OE/VPP CE O0 O1 O2 O3 O4 O5 O6 O7 9 10 11 13 14 15 16 17

16 kbit 2 kbyte

2716

2732
32 kbit 4 kbyte

2764

64 kbit 8 kbyte

PGM and VPP are used to programming

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27XXX EPROM
U7

U4 10 9 8 7 6 5 4 3 25 24 21 23 2 26 22 27 20 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 OE PGM CE VPP D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 22 20 1

U5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE CE VPP D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19

10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 22 20 28

U6 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE/VPP CE VCC O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 OE PGM CE VPP

D0 D1 D2 D3 D4 D5 D6 D7

13 14 15 17 18 19 20 21

27128

27256

128 kbit 16 kbyte

256 kbit 32 kbyte

27512

512 kbit 64 kbyte

Microprocessors

1024 kbit 128 kbyte

27010

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28XX E2PROM
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 OE WE CE VCC D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21

8 7 6 5 4 3 2 1 23 22 19 20 21 18 24

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 OE WE CE VCC

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

9 10 11 13 14 15 16 17

10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 28

A0 I/O0 A1 I/O1 A2 I/O2 A3 I/O3 A4 I/O4 A5 I/O5 A6 I/O6 A7 I/O7 A8 A9 RDY /BUSY A10 A11 A12 OE WE CE VCC

11 12 13 15 16 17 18 19 1

10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 22 27 20 28

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 OE WE CE VCC

D0 D1 D2 D3 D4 D5 D6 D7

11 12 13 15 16 17 18 19

12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 24 31 22 32

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 OE WE CE VCC

D0 D1 D2 D3 D4 D5 D6 D7

13 14 15 17 18 19 20 21

2816
16 kbit 2 kbyte

64 kbit 8 kbyte

2864

28256
256 kbit 32 kbyte

28010

28040

1026 kbit 128 kbyte

4096 kbit 512 kbyte

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Microprocessors

RAM (Random Access Memory)

P can read the data from RAM quickly P can write new data to RAM quickly RAM forgets its data if power is turned off Two type is available :
Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.

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Microprocessors

RAM(Static)
A0 A1
m+1 bit Address

D0 D1 D2

A2 Am

Capacity :

m 1

2m1 (n 1)
RAM

n+1 bit Data

Dn

RD : Read signal connect to MemRD of P

WR : Write signal connect to MemWR of P CS : Chip Select to Address decoder
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Data bus is Bidirectional

CS

WR

RD

Microprocessors

Static RAM

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Microprocessors

Dynamic RAM

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Microprocessors

Dynamic RAM
Write : Charge bitline HIGH or LOW and set wordline HIGH
Read : Bit line is precharged to a voltage halfway between HIGH and LOW and then the word line is set HIGH. Sense Amp Detects change Reads are destructive (Must follow with a write) Address Buffer

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Microprocessors