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Chapter 16 Control Unit Operation
No HW problems on this chapter. It is important to understand this material on the architecture of computer control units, and microprogrammed control units.
Basic Elements of Processor ALU Registers Internal data pahs External data paths Control Unit
A Simple Computer & its Control Unit
Instruction Micro-Operations A computer executes a program of instructions (or instruction cycles) Each instruction cycle has a number to steps or phases:
Fetch, Indirect (if specified), Execute, Interrupt (if requested)
These can be seen as micro-operations

Each step does a modest amount of work Atomic operation of CPU
Constituent Elements of its Program Execution
Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops
Control Signals
Clock
One micro-instruction (or set of parallel microinstructions) per clock cycle
Instruction register
Op-code for current instruction Determines which micro-instructions are performed
Flags
State of CPU Results of previous operations
From control bus

Interrupts Acknowledgements
Control Signals - output Within CPU

Cause data movement Activate specific functions
Via control bus

To memory To I/O modules
Flowchart for Instruction Cycle
Fetch - 4 Control Registers Utilized Program Counter (PC)

Holds address of next instruction to be fetched
Memory Address Register (MAR)

Connected to address bus Specifies address for read or write op
Memory Buffer Register (MBR)

Connected to data bus Holds data to write or last data read
Instruction Register (IR)

Holds last instruction fetched
Fetch Cycle
Address of next instruction is in PC Address (MAR) is placed on address bus t1: MAR (PC) Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR t2: MBR (memory) PC incremented by 1 (in parallel with data fetch from memory) PC (PC) +1 Data (instruction) moved from MBR to IR t3: IR (MBR) MBR is now free for further data fetches
Fetch Cycle
Fetch Cycle: t1: MAR (PC) t2: MBR (memory) PC (PC) +1 t3: IR (MBR)
Fetch Cycle Let Tx be the time unit of the clock. Then: t1: MAR (PC) t2: MBR (memory) PC (PC) +1 t3: IR (MBR)
Is this equally correct? t1: t2: t3: Why?
MAR (PC) MBR (memory) PC (PC) +1 IR (MBR)
Basic Rules for Clock Cycle Grouping Proper sequence must be followed
MAR (PC) must precede MBR (memory)
Conflicts must be avoided

Must not read & write same register at same time MBR (memory) & IR (MBR) must not be in same cycle
Also: PC (PC) +1 involves addition

Use ALU ? May need additional micro-operations
Indirect Cycle
Indirect Cycle: t1: MAR (IRaddress) t2: MBR (memory) t3: IRaddress (MBRaddress)
IR is now in same state as if direct addressing had been used (What does this say about IR size?)
Interrupt Cycle
Interrupt Cycle: t1: t2: MBR MAR PC t3: memory (PC) save-address routine-address (MBR)
This is a minimum. May be additional micro-ops to get addresses N.B. saving context is done by interrupt handler routine, not microops
Execute Cycle: ADD R1, memory
Execute Cycle: ADD R1, X t1: t2: t3: MAR (IRaddress) MBR (memory) R1 R1 + (MBR)
Different for each instruction Note no overlap of micro-operations
Execute Cycle: ISZ X
Execute Cycle: ISZ X t1: t2: t3: t4:
(inc and skip if zero)
MAR (IRaddress) MBR (memory) MBR (MBR) + 1 memory (MBR) if (MBR) == 0 then PC (PC) + 1
Notes:
if is a single micro-operation Micro-operations done during t4
Execute Cycle: BSA X
Execute: BSA X t1:
(Branch and Save Address)
BSA X - Branch and save address

Address of instruction following BSA is saved in X Execution continues from X+1
MAR (IRaddress) MBR (PC) t2: PC (IRaddress) memory (MBR) t3: PC (PC) + 1
Control Signals
Control Unit with Decoded Inputs
Internal Organization Usually a single internal bus Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU
Hard Wired Control Unit The Cycles (Fetch, Indirect, Execute, Interrupt) are constructed as a State Machine The Individual instruction executions can be constructed as State Machines
Common sections can be shared. There is a lot of similarity
One ALU is implemented. All instructions share it
State Machine
Combinational logic
Determine outputs at each state. Determine next state.
Storage elements
Maintain state representation.
State Machine
Inputs
Combinational Logic Circuit Storage Elements
Outputs
Clock
State Diagram
Shows states and actions that cause transitions between states.
Example State Machine

Inputs
Outputs
Next States
Master-slave flipflops
Problems With Hard Wired Designs Sequencing & micro-operation logic gets complex Difficult to design, prototype, and test Resultant design is inflexible, and difficult to build upon (Pipeline, multiple computation units, etc.) Adding new instructions requires major design and adds complexity quickly.
Chapter 17 Micro-programmed Control
Control Unit Organization

The Control Memory contains sequences of microinstructions that provide the control signals to execute instruction cycles, e.g. Fetch, Indirect, Execute, and Interrupt.
Tasks of Control Unit: Microinstruction sequencing Microinstruction execution
May be expected to complete instruction execution in 1 clock cycle. How is this possible?
Recall: Micro-sequencing
Simple Control Memory

I1-I4 Control Memory addresses O1-O16 Control Signals
Example of Control Memory Organization

Microinstructions: Generate Control Signals
Provide Branching Do both
Typical Microinstruction Formats
Horizontal vs Vertical Microprogramming Horizontal Microprogrammed

Unpacked Hard Direct
Vertical Microprogrammed
Packed Soft Indirect
Microinstruction Encoding Direct Encoding
Microinstruction Encoding Indirect Encoding
Horizontal Micro-programming
Wide control memory word High degree of parallel operations possible Little encoding of control information Fast
Vertical Micro-programming
Width can be much narrower Control signals encoded into function codes need to be decoded More complex, more complicated to program, less flexibility More difficult to modify Slower
Typical Microinstruction Formats
Next Address Decision Depending on ALU flags and control buffer register:
Get next instruction
Add 1 to control address register
Jump to new routine based on jump microinstruction

Load address field of control buffer register into control address register
Jump to machine instruction routine

Load control address register based on opcode in IR
Microprogrammed Control Unit
Advantages and Disadvantages of Microprogramming

Advantage: Simplifies design of control unit
Cheaper Less error-prone Easier to modify
Disadvantage: Slower
Design Considerations Necessity of speed Size of microinstructions Address generation

Branches
Both conditional and unconditional Based on current microinstruction, condition flags, contents of IR Based on format of address information
+ Two address fields + Single address field + Variable format
Address Generation
Explicit Two-field Unconditional Branch Conditional branch Mapping Addition Residual control Implicit
Branch Control: Two Address Fields

Branch based upon: Instruction Opcode Address 1 Address 2
Does require a wide microinstruction, but no address calculation is needed
Branch Control: Single Address Field

Branch based upon: Next instruction Address Opcode
Does require more circuitry, e.g. adder
Branch Control: Variable Format

One bit determines microinstruction format: Control signal format Branch format
Does require even more circuitry, and is slowest.

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Chapter 16 Control Unit Operation

A Simple Computer & its Control Unit

These can be seen as micro-operations

Constituent Elements of its Program Execution

From control bus

Control Signals - output Within CPU

Via control bus

Flowchart for Instruction Cycle

Fetch - 4 Control Registers Utilized Program Counter (PC)

Memory Address Register (MAR)

Memory Buffer Register (MBR)

Instruction Register (IR)

MAR (PC) MBR (memory) PC (PC) +1 IR (MBR)

Conflicts must be avoided

Also: PC (PC) +1 involves addition

Execute Cycle: ADD R1, memory

Different for each instruction Note no overlap of micro-operations

Execute Cycle: ISZ X

Execute Cycle: ISZ X t1: t2: t3: t4:

(inc and skip if zero)

Execute Cycle: BSA X

Execute: BSA X t1:

(Branch and Save Address)

BSA X - Branch and save address

Control Unit with Decoded Inputs

One ALU is implemented. All instructions share it

Combinational Logic Circuit Storage Elements

Example State Machine

Chapter 17 Micro-programmed Control

Control Unit Organization

Tasks of Control Unit: Microinstruction sequencing Microinstruction execution

Simple Control Memory

Example of Control Memory Organization

Typical Microinstruction Formats

Horizontal vs Vertical Microprogramming Horizontal Microprogrammed

Microinstruction Encoding Direct Encoding

Microinstruction Encoding Indirect Encoding

Typical Microinstruction Formats

Jump to new routine based on jump microinstruction

Jump to machine instruction routine

Microprogrammed Control Unit

Advantages and Disadvantages of Microprogramming

Design Considerations Necessity of speed Size of microinstructions Address generation

Branch Control: Two Address Fields

Does require a wide microinstruction, but no address calculation is needed

Branch Control: Single Address Field

Does require more circuitry, e.g. adder

Branch Control: Variable Format

Does require even more circuitry, and is slowest.

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