Introduction to Integrated Circuit Technology

By Prof. Vishwas V. Patange Shree TuljaBhavani College Of Engineering, Tuljapur.

Basic Concepts:

Current:

Voltage:

Flow of Electrons Carrying Electric Charge.

Resistance:

Conductor:

A material that readily supports the flow of electric current.

Contd

Insulator:

A material that blocks the flow of electric current.

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IC Elements & their functions:

Resistors:

Resists current flow. Stores charge. Allows current to flow in only one direction. Switches and or amplifies current.
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Capacitors:

Diodes:

Transistors:

Semiconductor:

Its a material that may act as a conductor or as an insulator depending on the conditions. Semiconductors may be made more conductive by adding other impurity elements to it. The ability to do it selectively i.e. adding impurity to one part of the semiconductor and not other parts is enables IC fabrication to take place.
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Integrated Circuit Manufacturing Overview:

1. Starting Substrate:

The starting substrate is purchased by virtually all major IC producers.

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2. Wafer Fabrication:

It is the process of fabricating number of ICs on the surface of the wafer simultaneously.

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3. Wafer Sort / Test:

Each IC (referred as die) on the wafer surface is tested and bad die are marked with an ink dot or an electronic map. The bad die are discarded after the wafer is sawn up.
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4. Packaging:

The wafer is sawn up into individual die and the good die are assembled into protective packages.

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5. Mark & class/final test:

It is in order to insure that the die were not damaged during packaging. The packaged product is tested and marked with the product type.
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Silicon Wafers:

Silicon is an abundant material in earths crust & relatively easy to obtain & refine. Silicon used for IC fabrication is highly purified, grown into nearly perfect crystals & sliced up into discs called wafers (less than a millimeter thick & 100mm to 300mm in diameter). Silicon wafers are highly polished appearing mirror like, extremely flat & extremely clean at the start of fabrication.
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Contd

Wafers typically have a flat section ground on to one or more edges to mark how the crystal planes are oriented in the wafer.

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Contd

Wafers use a small notch in place of flat because flat may take away an unacceptable amount of wafer area on the larger wafers.

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Silicon Wafer manufacturing Process:

Pull Crystal Ingot

A small seed of single crystal silicon is dipped into a crucible of molten silicon. The crucible and seed are rotated in opposite directions & seed is slowly withdrawn from the crucible.

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Ingot grind

The silicon crystal ingot is ground to create a consistent diameter of the whole ingot.

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Saw off ingot ends

The two ends of the saw ingot are sawn off using a diamond saw.

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Saw up the ingot into wafers

The ingot is sawn up into wafers each approximately mm to mm in thickness and 100 mm to 300 mm in diameter.

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Edge grind wafers

The edges of the wafer are ground to round off the sharp edges. This may minimize the damaging of the wafer edges during subsequent processing.
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Lap Wafers

A process called lapping is used to flatten out the wafers and ensures the two wafer faces are parallel.

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Damage Removal Etch

A special wet etch is used to etch off the surface damage left from lapping.

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Polish

The polish step removes the final residual damage layer on the wafers and creates a mirror polish surface.

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Final Clean

The final clean step removes any contaminants left on the wafer surface from the previous steps.

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Photolithography

At the heart of the wafer fabrication process is a photolithography. Photolithography creates patterns of photoresists (a liquid chemical that resists etching process). Its working is as follows:

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Working of Photolithography:

Surface Prime:

Its a surface treatment to drive off moisture & improve adhesion of photoresist.

Coat:

A small amount of photoresist is dispensed onto the center of the wafer & then spun at very high speed to produce uniform thin film.
This process is done to stabilize the film.
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Prebake:

Contd

Exposure: The exposure step photographically transfers a pattern from a reticle (glass surface with patterns of opaque transparent areas) to the photoresist coating on the wafer surface Post Exposure Bake: This process is required to complete the chemical reaction initiated by exposure. Develop: Wash away the photoresist wherever light exposed a pattern into the photoresist & leave the photoresist wherever the light was blocked
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Contd

Postbake:

Bake the photoresist to stabilize the film prior to subsequent processing.

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Ion Implantation:

Impurities may be used to change the electrical properties of silicon. Ion implantation is currently the most commonly used method for introducing impurities to silicon. In an ion implanter, impurities to introduced to silicon are ionized. A high voltage electric field is then applied to accelerate the ions to very high energy. Thus, because of high energy ions penetrate on to the surface of silicon and gets implanted on it.

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Contd

This process can be made selective by using a photoresistive pattern to block impurity ions from reaching other areas on silicon surface.

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Etching:

In the early days, wet etching (liquid chemical) was used. In most cases of wet etching, it etches in all directions & underneath the etch of the photoresist too. So, now a days, etching process used excited gas molecules to performing etching & can achieve faster etching in one direction.
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Contd

When line widths are relatively large, isotropic etching is acceptable. But as line widths shrink isotropic etching can result in complete undercutting of the feature being printed.

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Chemical Vapor Deposition:

In CVD process, ammonia gas and dichlorosilane are reacted to produce a deposited solid film of silicon nitride. Gaseous by products (HCl, H2, Cl2 & N2) are then pumped away
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IC thin films commonly deposited by CVD:

Sputter Deposition:

In the sputtering process, argon gas is excited by a high energy field to split up into positively charged argon ions and free electrons. An electric field attracts the argon ions towards the target made out of the material to be deposited.
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Chemical Mechanical Planarization:

CMP process combines chemical & mechanical material removal to produce fully planar surfaces. It is illustrated in the figure below.

Contd

The exact mechanism of CMP depends on the material to be polished & polishing slurry used. In general, chemical reaction is used to soften up the film being removed & then mechanical abrasion from the slurry particles removes the material. Its advantage is that, only specific areas on the film are attacked.
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Putting it all together:

The end result is number of ICs together on the single wafer. Each IC may have tens of millions or even over a 100 million circuit elements. Many ICs now in production have over 1 billion transistors & 1 billion capacitors on a single IC.
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END.

Feel free to contact me on: 9028 91 91 79 [email protected]

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