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Interleaved Memory

Memory interleaving divides memory into multiple modules and maps addresses across the modules in a way that overlapping memory accesses can hide latency. There are two main approaches: high-order interleaving which maps sequential addresses to different modules, and low-order interleaving which maps them to the same module. Synchronized and independent access organizations allow pipelining memory operations across modules to improve performance over non-interleaved designs. However, interleaved memories require complex control and have poor fault tolerance if a module fails.

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513 views17 pages

Interleaved Memory

Memory interleaving divides memory into multiple modules and maps addresses across the modules in a way that overlapping memory accesses can hide latency. There are two main approaches: high-order interleaving which maps sequential addresses to different modules, and low-order interleaving which maps them to the same module. Synchronized and independent access organizations allow pipelining memory operations across modules to improve performance over non-interleaved designs. However, interleaved memories require complex control and have poor fault tolerance if a module fails.

Uploaded by

K.R.Raguram
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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MEMORY INTERLEAVING

15/08/2012

CA & PP Assignement Presentation

Introduction
Principle of memory interleaving

Dividing memory into a number of memory modules and arranging different sets of addresses to different modules
In our memory Designs , If we want a larger memory, we simply add more memory modules. This modular design is useful in incrementally expanding the memory.

This design however, has one major disadvantage. Since sequential addresses are mapped to the same memory module, we have wait for the memory access time for each word we read from the memory module.
15/08/2012 CA & PP Assignement Presentation 2

Normal memory address mapping

In the memory designs we described so far, we divided the nbit memory address bits into two parts:
The higher- order r bits are used to identify a memory module and lower order m bits are used to specify a locations in the memory module. n= r+m. this technique is sometimes called high-order interleaving.( fig-a)
15/08/2012 CA & PP Assignement Presentation 3

Interleaved memory
To provide overlapped access to address, we have to resort to low-order interleaving, as shown in above fig- b. In this design, the lower- order r bits are used to identify a memory module and higher order m bits are used to specify a location. We normally use the term interleaved memory to mean low-order interleaving .

15/08/2012

CA & PP Assignement Presentation

Memory interleaving Concept


High-performance computers typically use interleaved memories to improve access performance. Essentially, these memories allow overlapped access to hide the memory latency.

The key idea is to design the memory system with multiple banks (similar to our memory modules) and access all banks simultaneously so that access time can be overlapped.

15/08/2012

CA & PP Assignement Presentation

Memory interleaving Concept


In these designs, the memory modules are referred to as memory banks. In interleaved memories, memory address are mapped on a round- robin basis. Thus in a B-bank design, address 0 is mapped to bank 0, address 1 to bank 1, and so on. A memory address addr is mapped to memory bank b = addr MOD B.

We can implement interleaved memories using two possible designs: synchronized access organization & independent access organization
15/08/2012 CA & PP Assignement Presentation 6

Example mappings

15/08/2012

CA & PP Assignement Presentation

Block Diagram of Synchronized Access Organization

15/08/2012

CA & PP Assignement Presentation

Synchronized Access Organization


In this organization, the upper m bits are presented to all memory banks simultaneously. Above fig shows design for a four- bank interleaved memory. As before, it is assumed that the memory access takes four cycles. Thus in four cycles, we will have four data words from the four banks, these data words are latched into four tristate memory data registers (MDRs). We can transfer these four words in four clocks by selecting the appropriate MDR from the lower order bits using a 2-to4 decoder. Simultaneously, we can present the next address to the memory bank to initiate the next memory access cycle. Thus, by the time we transfer the four words from the first cycle , next four words from the second access cycle
15/08/2012 CA & PP Assignement Presentation 9

Non-interleaved memory & interleaved memory access


The figure 1 shows the non- interleaved memory access takes four clocks for each access,

Fig-1 On the other hand ( Figure-2) interleaved memory ,transfers the first word ( WO) after four cycle, After that, one word is transferred every clock cycle. Thus, to transfer eight words, we need 12 clock cycles.

Non-interleaved memory need 32 clocks.


15/08/2012

Fig-2

CA & PP Assignement Presentation

10

Block diagram of Independent Access Organization

15/08/2012

CA & PP Assignement Presentation

11

Independent Access Organization


Draw back with synchronized design is that it does not efficiently support access to non- sequential access patterns. The independent access organization allows pipelined access.

In order to support this kind of access, we have provide each memory bank with a memory address register(MAR) to latch the address that the bank should use. In our example, we can load four different addresses for the four banks. In this design, we do not need the MDR registers to latch the data. Instead, the data are read directly from the memory bank.
15/08/2012 CA & PP Assignement Presentation 12

Independent Access Organization


Independent design still provides the same kind of pipelined access as the synchronized access design. To see this, lets trace the first few data transfers from addresses 100, 81, 54, 31,108, and 121. We can use (address MOD 4) to determine the memory bank number. The first address 100 is sent to bank 0. Once this address is latched in the MAR of bank 0, this bank can initiate the memory access cycle. During the next clock cycle, address 81 is latched into the MAR of bank 1.

15/08/2012

CA & PP Assignement Presentation

13

Independent Access Organization


The next two addresses are sent to banks 2 and 3. After latching the address in the MAR of bank 3, data from bank 0 are available. So the next clock cycle is used to transfer the data from bank 0. We can now load the new address (108) in the MAR register of bank 0.

15/08/2012

CA & PP Assignement Presentation

14

Independent Access Organization


Similarly, during the next clock, data from bank 1 are transferred, and a new address (121) is latched into the MAR of bank 1. This process repeats to provide pipelined access for arbitrary addresses. Of course, this organization also works for the sequential addresses.

15/08/2012

CA & PP Assignement Presentation

15

Drawbacks
Why do we see interleaved memories only in highperformance computers? Why not in our PCs? One reason is that interleaved memories involve complex design. We have seen some of this complexity in our examples. We need extra registers (MAR or MDR) to latch addresses or data. What we have not shown in these examples is the control circuit needed to transfer data and to load addresses.
Another major reason is that interleaved memories do not have good fault-tolerance properties. That is, if one bank fails, we lose the entire memory.
15/08/2012 CA & PP Assignement Presentation 16

THANK YOU

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CA & PP Assignement Presentation

17

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