D.Murali Krishna Sr. Asst. Prof., Dept.

of ECE

Introduction:
8051 has interrupt handling mechanism for The masking of interrupt source Priority assignment Use of vector address for ISR The mechanism uses the bits at the IE (Interrupt

Enable) and IP (Interrupt Pointer) registers.

Interrupt Handling structure of an MCU

 Identification of the interrupts source. Enabling (or) disabling of the sources. Finding (or) generating the address of ISR Priority assignments, default assignments, increasing

(or) lowering priorities as per need.

Routine, Interrupt & ISR

Assume program or routine is executing and running a

task. The running task is at the foreground program. The foreground program may call another routine at some point of time using an instruction (Eg: ACALL, LCALL) The CALL instruction executes as follows
Saves the PC at the stack and re-adjusts the stack

pointer Gets the address of the called-routine The return instruction restores the PC from the stack and re-adjusts the stack pointer

 On an interrupt, the execution of an instructions starts

for a service routine. This routine is called an Interrupt Service Routine (ISR)

Servicing of Interrupts in 8051:

When interrupt occurs the CPU does the follg. actions Completes current instruction. When EA=1, and the source which is unmasked by setting appropriate bit at IE=1, the servicing of that source will occur as follows.

CPU pushes on to the internal stack two CPU registers PCH and PCL Reset EA=0 momentarily and the sets it again to 1 automatically at the ISR. CPU sets the PC bits as per the corresponding ISR_VECTADDR After the first instruction at the ISR, servicing of any further interrupts from any lower priority interrupt are the only ones disabled until RETI executes and returns from the ISR occurs.

 A Vector address is a memory address where the CPU

changes the direction of program flow automatically for the execution of the ISR. An action on interrupt from a source can occur only whenever the CPU has been previously enabled by program to respond to that interrupt

Identification of an Interrupt Source:

When an interrupt source activates, a FLAG enables

which is identification to the processor. A Flag can be either at a register called

Interrupt status register (or) at the Interrupt pending register (or) may coexist with the Control bits in the control register.

Example
TI & RI (bits of SCON) TF1 & TF0 (bits of TCON) IE1 & IE0 (bits of TCON)

Address of Interrupt Service Routine (ISR):

How does the CPU find (or) evaluate the ISR_ADDR?

There are 3 methods Direct Access Method Vector Address Method Vector Address for ISR pointer method

Direct Access Method

Interrupt source itself provides the address to the CPU.

The source device puts the address through the data

bus. For Eg., an external circuit, which sends an interrupt message on INTR also send the ISR_ADDR in the subsequent interrupt acknowledgement cycles at INTA pin.

Vector Address Method

An interrupt source auto generates at the CPU vector

address, ISR_VECTADDR. ISR_VECTADDR is a memory address where the ISR is (or) where it executes a call (or) jump instructions to the actual location of the ISR

Vector Address for ISR pointer method

Interrupt source provides a vector address pointer,

ISR_VECTADDR_Pointer to the CPU. ISR_VECTADDR_Pointer is an address from where the CPU fetches the ISR_ADDR, the address of the ISR for the source. For internal interrupts, the ISR_VECTADDR_Pointer automaticllay generates as per the interrupt type. The external interrupt (Source) can also put the address ISR_VECTADDR_Pointer through the data bus.

Interrupt Latency and deadline:

Interrupt Latency can be defined as the interval b/w the

interrupt event and the start of the ISR. It is defined as maximum permissible interrupt latency plus execution interval of the ISR.
Ex: If a timer overflows at T0 and its routine initiates at T1,

then

interrupt latency , Tlat= T1-T0. If it is serviced latest by t2, interrupt deadline, Td=T2-T0.
One way to measure the real-time performance of a system is

Interrupt Latency

Multiple sources of interrupts:

Hardware interrupts related to internal devices: Timer overflows (8051) Input capture interrupts (8052, 68HC11/12) Out compare interrupts (68HC11/12) End of serial transmission and reception of a character (8051, 68HC11/12, 80196) Interrupt when Serial buffer is full (80196) Interrupt on start of ADC and at the end of conversion.

Hardware interrupts related to external devices:

They depend on the CPU.

Method of finding address example Direct address access

INTR pin of 8086

Vector address method RST 5.5, 6.5, 7.5 pins in 8085, INT0 & INT1 of 8051 Vector address for ISR pointer method NMI pin (8086)

Software related interrupts:

Due to errors or instructions

Interrupt Software instruction

RST 1-7 inst. (8085) INT type (8086) INTO (8086) SWI (68HC11/12)

Errors
divide by zero (type 0),
illegal op code (type 6), overflow (type 4)

Non maskable interrupt sources:

All Interrupts of 8051 are maskable

Processor 80x86
NMI pin

68HC11/12 clock monitor failure TRAP external XIRQ pin

Enabling (or) disabling of the sources

There are different maskable interrupts in 8051. An MCU may require the follg. during the execution of

a foreground program
Disable all interrupt sources to the running program Clearing IE.7 bit, all interrupts will be disabled. IE.7 is thus also called primary level enable bit. Enable interrupt structure responses but masks certain

specific source(s) or source group(s).

For Eg., IE.6-IE.0 bits at the IE reg. do this Setting IE.7=1, enables all interrupt event responses by the interrupt structure of 8051 and clearing IE.4=0 masks the serial port interface interrupts. IE.4 is called SI mask bit or secondary level enable bit

 There are certain interrupts that can be masked, so

those certain events do not respond by the interrupt handling structure. All maskable interrupt sources can also be masked by a single enabling/disabling bit.
Problem1: set the INT0 as negative edge triggered &

INT1 as level0 activated. Enable INT0 & INT1 only and mask all remaining ones. SETB IT0 CLR IT1 MOV IE, #85H

Problem2: Modify the codes to enable INT0 & INT1without effecting the other mask bit. ORL IE, #85H

Problem3: Run any program without any interruption with highest priority. Before the ISR program, CLR EA At the end of procedure, SETB EA

Polling to determine the interrupt sources & assignment of priorities:

Occurrence of event is identifiable from a bit (or) bits in

the
Status register

and/or in the Interrupt pending register.

Several interrupt events can occur in quick successions,

there are the follg. Possibilities. Several interrupts occurring at the same time during the execution of set of instructions & either all (or) a few of these are to be serviced in a certain order of priority A program is under execution and an interrupt occurs which happens to be a critical ISR, which should be executed on priority

 An interrupt is under servicing by a temporary

diversion to an ISR, and at that instant, another interrupt occurs which should also be serviced as per precedence assigned. 2 possibilities exist
Either the second is serviced only after the completion

of the first interrupt Either the second is to be serviced immediately, giving precedence over the first

 Issues: Several interrupts serviced under priority

User assignable priority Default priority Interrupt Default priority INT0 1 TF0 2 INT1 3 TF1 4 TI/RI 5 Critical ISR

 Types of Polling Procedures:

Preemptive method: vectored priority method with diversion to a higher priority ISR than present one 8051 Linux 2.6 Non-Preemptive method: vectored priority method with no permissible diversion after each end of ISR 68HC11/12 Linux 2.4

Problem: There are 4 interrupts 1,2,3 &4 in priority order. Let interrupt 3 be under service and interrupt 4 is pending since past 1ms. Now, if a higher priority interrupt 1 occurs at time t having execution time 5ms. Calculate the latency of interrupt 4.

Preemptive method

Non-Preemptive method

Interrupt structure in INTEL 8051

An input 1 for 2 machine cycles at the RESET input

causes the program to start from PC=0000H The SFRs are all zeros The IP, except its 7th bit, loads all bits 0s User assigned priorities are initially set to LOW The default SP=07H, WDCON = A5H to disable watchdog timer

8051 provides seven sources of interrupts

If EA bit in the IE register is reset, then none of the

source group is recognized

 If EA=1, then source group is recognized and serviced. When interrupt source is enabled for the service, The EA bit is temporarily made 0 till the first instruction end

Default assigned priority wise source groups

Group 1 INT0 (External) interrupt IE0 only (0003H) Priority can be define by PX0 bit (HIGH or LOW) If EA=1 & IE.0 bit is 1 then IE0 interrupt is identified on

Occurrence of a ve edge provided by the bit IT0 at the TCON is set Occurrence of a level 0 if the bit, IT0 is reset.

This source is maskable through IE.7 and IE.0 bits

Group 3 ( In selected family members) SI device Serial Synchronous port Interface Vector address (0053H) Priority can be define by PS1 (Ip.6) bit (HIGH or LOW) When EA=1 & if this bit is 1 then an SI interrupt can happen on occurrence of the first bit. The 1st bit interrupt enables a read of the address of the slave using serial clock and data lines. The Occurrence of this interrupt is identified by 1 at the 7th bit in SIINT register. This bit when sets does not clear automatically on start of the interrupt service.

Group 4 Timer 0 overflow identified by the TF0 (000Bh) Priority can be define by PT0 (Ip.1) bit (HIGH or LOW) When EA=1 & IE.1=1, timer0 overflow TF0 bit sets 1 on overflow event and automatically resets to 0 on start of this interrupt source.

Group 5 INT1 (External) interrupt IE1 only (0013H) Priority can be define by PX1 bit (HIGH or LOW) If EA=1 & IE.2 bit is 1 then IE1 interrupt is identified on

Occurrence of a ve edge provided by the bit IT1 at the TCON is set Occurrence of a level 0 if the bit, IT1 is reset.

This source is maskable through IE.7 and IE.2 bits

Group 6 Timer 1 overflow identified by the TF1 (001Bh) Priority can be define by PT1 (Ip.3) bit (HIGH or LOW) If EA=1 & IE.3=1, timer1 overflow TF1 bit sets 1 on overflow event and automatically resets to 0 on start of this interrupt source.

Group 7 The SI serial port synchronous and synchronous UART communication interrupts, TI & RI are in this group When EA=1 & ES=1 the transmit data to be completed is identified by the TI. When interrupt is enabled, the receive data completion event is identified by RI. PS bit (PS.4 at the IP) defines the priority Baud rate is programmed by T1 overflow interval or T2 overflow intervals