Lecture 24 Design for Testability (DFT): Partial-Scan & Scan Variations

Definition

Partial-scan architecture

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Historical background Cyclic and acyclic structures Partial-scan by cycle-breaking S-graph and MFVS problem Test generation and test statistics Partial vs. full scan Partial-scan flip-flop Random-access scan (RAS) Scan-hold flip-flop (SHFF) Summary
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Partial-Scan Definition

A subset of flip-flops is scanned. Objectives: Minimize area overhead and scan sequence length, yet achieve required fault coverage Exclude selected flip-flops from scan:

Allow automation:

Improve performance Allow limited scan design rule violations

Shorter scan sequences

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In scan flip-flop selection In test generation

Partial-Scan Architecture
PI Combinational circuit PO

CK1 FF FF CK2 SFF SCANOUT

TC
SFF SCANIN
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History of Partial-Scan

Scan flip-flop selection from testability measures, Trischler et al., ITC-80; not too successful. Use of combinational ATPG: Agrawal et al., D&T, Apr. 88

Functional vectors for initial fault coverage Scan flip-flops selected by ATPG Balanced structure Sometimes requires high scan percentage

Gupta et al., IEEETC, Apr. 90

Use of sequential ATPG: Cheng and Agrawal, IEEETC, Apr. 90; Kunzmann and Wunderlich, JETTA, May 90

Create cycle-free structure for efficient ATPG

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Difficulties in Seq. ATPG

Poor initializability. Poor controllability/observability of state variables. Gate count, number of flip-flops, and sequential depth do not explain the problem. Cycles are mainly responsible for complexity. An ATPG experiment:
Circuit TLC Chip A Number of gates 355 1,112 Number of flip-flops 21 39 Sequential depth 14* 14 ATPG CPU s 1,247 269 Fault coverage 89.01% 98.80%

* Maximum number of flip-flops on a PI to PO path

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Benchmark Circuits
Circuit PI PO FF Gates Structure Sequential depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 14 18 529 Cycle-free 4 1242 1239 0 3 0 99.8 100.0 3 313 10 s1238 14 14 18 508 Cycle-free 4 1355 1283 0 72 0 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -1506 1379 2 30 97 91.6 93.4 28 559 19183

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Cycle-Free Example
Circuit
F2 2 F1 Level = 1 F2 2 F1 Level = 1 F3 3 dseq = 3 F3 3

s - graph

All faults are testable. See Example 8.6.

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Relevant Results

Theorem 8.1: A cycle-free circuit is always initializable. It is also initializable in the presence of any non-flip-flop fault. Theorem 8.2: Any non-flip-flop fault in a cycle-free circuit can be detected by at most dseq + 1 vectors. ATPG complexity: To determine that a fault is untestable in a cyclic circuit, an ATPG program using nine-valued logic may have to analyze 9Nff time-frames, where Nff is the number of flip-flops in the circuit.

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A Partial-Scan Method

Select a minimal set of flip-flops for scan to eliminate all cycles. Alternatively, to keep the overhead low only long cycles may be eliminated. In some circuits with a large number of self-loops, all cycles other than self-loops may be eliminated.

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The MFVS Problem

For a directed graph find a set of vertices with smallest cardinality such that the deletion of this vertex-set makes the graph acyclic. The minimum feedback vertex set (MFVS) problem is NP-complete; practical solutions use heuristics. A secondary objective of minimizing the depth of acyclic graph is useful.
3 3 L=3 1 2 4 L=1 A 6-flip-flop circuit s-graph
10

L=2

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Test Generation

Scan and non-scan flip-flops are controlled from separate clock PIs:

Normal mode Both clocks active Scan mode Only scan clock active
Scan flip-flops replaced by PI and PO Seq. ATPG program used for test generation Scan register test sequence, 001100, of length nsff + 4 applied in the scan mode Each ATPG vector is preceded by a scan-in sequence to set scan flip-flop states A scan-out sequence is added at the end of each vector sequence

Seq. ATPG model:

Test length = (nATPG + 2) nsff + nATPG + 4 clocks

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Partial Scan Example

Circuit: TLC 355 gates 21 flip-flops

Max. cycle length Depth* ATPG CPU s Fault sim. CPU s Fault cov. ATPG Test seq. vectors length

Scan flip-flops

0
4 9

4
2 1

14
10 5

1,247
157 32

61
11 4

89.01%
95.90% 99.20%

805
247 136

805
1,249 1,382

10
21

1
0

3
0

13
2

4
2

100.00%
100.00%

112
52

1,256
1,190

* Cyclic paths ignored

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Test Length Statistics

Circuit: TLC
Number of faults
200
100 0 200 100 0 200 100 0

Without scan
Test length

50

100

150

200

250

Number of faults

9 scan flip-flops
Test length

10

15

20

25

Number of faults

10 scan flip-flops
Test length 13

10

15

20

25

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Partial vs. Full Scan: S5378

Original Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II 200MHz processor Number of ATPG vectors Scan sequence length 2,781 179

Partial-scan
2,781 149 30 2.63% 4,603 65/79 93.7% 99.5% 727 s 1,117 34,691

Full-scan

2,781 0
179 15.66% 4,603 214/228 99.1% 100.0% 5s

0
0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 414

585 105,662

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Flip-flop for Partial Scan

Normal scan flip-flop (SFF) with multiplexer of the LSSD flip-flop is used. Scan flip-flops require a separate clock control:

Either use a separate clock pin Or use an alternative design for a single clock pin
D

MUX
SD TC CK TC

Master latch

Slave latch

SFF (Scan flip-flop)

CK
Normal mode
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Scan mode
15

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Random-Access Scan (RAS)

PI Combinational logic RAM CK TC SCANIN

PO

nff
bits SCANOUT SEL

Address decoder
ADDRESS ACK
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Address scan register log2 nff bits

16

RAS Flip-Flop (RAM Cell)

From comb. logic SCANIN

D
SD Scan flip-flop (SFF)

To comb. logic

CK
TC SCANOUT

SEL

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RAS Applications

Logic test: reduced test length. Delay test: Easy to generate single-inputchange (SIC) delay tests. Advantage: RAS may be suitable for certain architecture, e.g., where memory is implemented as a RAM block. Disadvantages:

Not suitable for random logic architecture High overhead gates added to SFF, address decoder, address register, extra pins and routing

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Scan-Hold Flip-Flop (SHFF)

D To SD of next SHFF

SD
TC CK SFF

HOLD

The control input HOLD keeps the output steady at previous state of flip-flop. Applications:

Reduce power dissipation during scan Isolate asynchronous parts during scan test Delay testing
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Summary

Partial-scan is a generalized scan method; scan can vary from 0 to 100%. Elimination of long cycles can improve testability via sequential ATPG. Elimination of all cycles and self-loops allows combinational ATPG. Partial-scan has lower overheads (area and delay) and reduced test length. Partial-scan allows limited violations of scan design rules, e.g., a flip-flop on a critical path may not be scanned.
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