Lecture 9 Combinational Automatic Test-Pattern Generation (ATPG) Basics

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Algorithms and representations Structural vs. functional test Definitions Search spaces Completeness Algebras Types of Algorithms
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Origins of Stuck-Faults

Eldred (1959) First use of structural testing for the Honeywell Datamatic 1000 computer Galey, Norby, Roth (1961) First publication of stuck-at-0 and stuck-at-1 faults Seshu & Freeman (1962) Use of stuckfaults for parallel fault simulation Poage (1963) Theoretical analysis of stuck-at faults

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Functional vs. Structural ATPG

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Carry Circuit

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Functional vs. Structural (Continued)

Functional ATPG generate complete set of tests for circuit input-output combinations 129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests augment with structural tests to boost coverage to 98+ %
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Definition of Automatic Test-Pattern Generator

Operations on digital hardware: Inject fault into circuit modeled in computer Use various ways to activate and propagate fault effect through hardware to circuit output Output flips from expected to faulty signal Electron-beam (E-beam) test observes internal signals picture of nodes charged to 0 and 1 in different colors Too expensive Scan design add test hardware to all flip-flops to make them a giant shift register in test mode Can shift state in, scan state out Widely used makes sequential test combinational Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence
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Circuit and Binary Decision Tree

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Binary Decision Diagram

BDD Follow path from source to sink node product of literals along path gives Boolean value at sink Rightmost path: A B C = 1 Problem: Size varies greatly with variable order

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Algorithm Completeness

Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test Untestable fault no test for it even after entire tree searched Combinational circuits only untestable faults are redundant, showing the presence of unnecessary hardware

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Algebras: Roths 5-Valued and Muths 9-Valued

Failing Good Symbol Meaning Machine Machine 0 D 1/0 1 1 D 0/1 0 Roths 0 0 0/0 0 Algebra 1 1 1/1 1 X X X/X X X G0 0/X 0 X G1 1/X 1 Muths 0 Additions F0 X/0 X 1 F1 X/1 X
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Roths and Muths Higher-Order Algebras

Represent two machines, which are simulated simultaneously by a computer program: Good circuit machine (1st value) Bad circuit machine (2nd value) Better to represent both in the algebra: Need only 1 pass of ATPG to solve both Good machine values that preclude bad machine values become obvious sooner & vice versa Needed for complete ATPG: Combinational: Multi-path sensitization, Roth Algebra Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault

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Exhaustive Algorithm

For n-input circuit, generate all 2n input patterns Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested

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Random-Pattern Generation

Flow chart for method Use to get tests for 6080% of faults, then switch to D-algorithm or other ATPG for rest

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Boolean Difference Symbolic Method (Sellers et al.)

g = G (X1, X2, , Xn) for the fault site fj = Fj (g, X1, X2, , Xn) 1 j m Xi = 0 or 1 for 1 i n
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Boolean Difference (Sellers, Hsiao, Bearnson)

Fj g Fj g

Shannons Expansion Theorem: F (X1, X2, , Xn) = X2 F (X1, 1, , Xn) + X2 F (X1, 0, , Xn) Boolean Difference (partial derivative): = Fj (1, X1, X2, , Xn) Fj (0, X1, , Xn)

Fault Detection Requirements: G (X1, X2, , Xn) = 1 = Fj (1, X1, X2, , Xn) Fj (0, X1, , Xn) = 1
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Path Sensitization Method Circuit Example

1 Fault Sensitization 2 Fault Propagation 3 Line Justification

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Path Sensitization Method Circuit Example

Try path f h k L blocked at j, since
there is no way to justify the 1 on i D D D 1 0 1 1

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Path Sensitization Method Circuit Example

Try simultaneous paths f h k L and
g i j k L blocked at k because D-frontier (chain of D or D) disappears
1 1

D
D D

1
D

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Path Sensitization Method Circuit Example

Final try: path g i j k L test found!
0 1

0
D D D

1 1

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Boolean Satisfiability

2SAT: xi xj + xj xk + xl xm = 0 . . . xp xy + xr xs + xt xu = 0 3SAT: xi xj xk + xj xk xl + xl xm xn = 0 . . . xp xy + xr xs xt + xt xu xv = 0
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Satisfiability Example for AND Gate

S ak bk ck = 0 (non-tautology) or P (ak + bk + ck) = 1 (satisfiability)

AND gate signal relationships: Cube: If a = 0, then z = 0 az If b = 0, then z = 0 bz If z = 1, then a = 1 AND b = 1 z ab If a = 1 AND b = 1, then z = 1 abz Sum to get: a z + b z + a b z = 0 (third relationship is redundant with 1st two)
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Pseudo-Boolean and Boolean False Functions

Pseudo-Boolean function: use ordinary + --

integer arithmetic operators Complementation of x represented by 1 x FpseudoBool = 2 z + a b a z b z a b z = 0 Energy function representation: let any variable be in the range (0, 1) in pseudo-Boolean function Boolean false expression: fAND (a, b, z) = z (ab) = a z + b z + a b z

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AND Gate Implication Graph

Really efficient Each variable has 2 nodes, one for each literal If then clause represented by edge from if literal to then literal Transform into transitive closure graph When node true, all reachable states are true ANDing operator used for 3SAT relations

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Computational Complexity

Ibarra and Sahni analysis NP-Complete (no polynomial expression found for compute time, presumed to be exponential) Worst case: no_pi inputs, 2 no_pi input combinations no_ff flip-flops, 4 no_ff initial flip-flop states (good machine 0 or 1 bad machine 0 or 1) work to forward or reverse simulate n logic gates a n Complexity: O (n x 2 no_pi x 4 no_ff)

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History of Algorithm Speedups

Algorithm Est. speedup over D-ALG Year (normalized to D-ALG time) D-ALG 1 1966 PODEM 7 1981 FAN 23 1983 TOPS 292 1987 SOCRATES 1574 ATPG System 1988 Waicukauski et al. 2189 ATPG System 1990 EST 8765 ATPG System 1991 TRAN 3005 ATPG System 1993 Recursive learning 485 1995 Tafertshofer et al. 25057 1997
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Analog Fault Modeling Impractical for Logic ATPG

Huge # of different possible analog faults in digital circuit Exponential complexity of ATPG algorithm a 20 flip-flop circuit can take days of computing Cannot afford to go to a lower-level model Most test-pattern generators for digital circuits cannot even model at the transistor switch level (see textbook for 5 examples of switch-level ATPG)
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