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VGA Interface Theoretical Overview

The document provides an overview of VGA interfaces and monitors. It describes how a VGA monitor displays pixels in a grid with at least 480 rows of 640 pixels each. It explains the timing of horizontal and vertical synchronization signals that control when each pixel and row is refreshed. Equations are given for calculating the timing of updating individual pixels, rows, and the full screen. The document also describes how a VGA interface allows a device like the Altera DE2 board to control an external monitor by manipulating red, green, blue, and synchronization signals. It presents a practical example of implementing a "virtual screen" in VHDL to move a white rectangle across a black background.

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89 views5 pages

VGA Interface Theoretical Overview

The document provides an overview of VGA interfaces and monitors. It describes how a VGA monitor displays pixels in a grid with at least 480 rows of 640 pixels each. It explains the timing of horizontal and vertical synchronization signals that control when each pixel and row is refreshed. Equations are given for calculating the timing of updating individual pixels, rows, and the full screen. The document also describes how a VGA interface allows a device like the Altera DE2 board to control an external monitor by manipulating red, green, blue, and synchronization signals. It presents a practical example of implementing a "virtual screen" in VHDL to move a white rectangle across a black background.

Uploaded by

Saeed Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VGA Interface Theoretical overview:

A standard VGA monitor consists of a grid of pixels that can be divided into rows and columns. A VGA monitor contains at least 480 rows, with 640 pixels per row, as shown in Figure 1. Each pixel can display various colours, depending on the state of the red, green, and blue signals.

Figure 1.
Each VGA driver has an internal clock that determines when each pixel is updated. This clock operates at the VGA-specified frequency of 25.175 MHz. The monitor refreshes the screen in a prescribed manner that is partially controlled by the horizontal and vertical synchronization signals. The monitor starts each refresh cycle by updating the pixel in the top left-hand corner of the screen, which can be treated as the origin of an XY plane (see Figure 1). After the first pixel is refreshed, the monitor refreshes the remaining pixels in the row. When the monitor receives a pulse on the horizontal synchronization, it refreshes the next row of pixels. This process is repeated until the monitor reaches the bottom of the screen. When the monitor reaches the bottom of the screen, the vertical synchronization pulses, causing the monitor to begin refreshing pixels at the top of the screen (i.e., at [0,0]). For the VGA monitor to work properly, it must receive data at specific times with specific pulses. Horizontal and vertical synchronization pulses must occur at specified times to synchronize the monitor while it is receiving colour data. Figures 2,3 shows the timing waveforms for the colour information with respect to the horizontal and vertical synchronization signals.

Figure 2.

Figure 3.
The frequency of operation and the number of pixels that the monitor must update determines the time required to updating each pixel, and the time required to update the whole screen. The following equations roughly calculate the time required for the monitor to perform all of its functions.

Tpixel = 1/fCLK = 1000/25.17539.722 ns TROW =A=B+C+D+E= (Tpixel 640 pixels) + row + guard bands 31.77 s Screens=O=P+Q+R+S = (TROW 480 rows) + guard bands 16.6 ms Where: Tpixel = Time required to update a pixel; fCLK= 25.175 MHz TROW = Time required to update one row Tscreen = Time required to update the screen B, C, E = Guard bands P, Q, S = Guard bands

The monitor writes to the screen by sending red, green, blue, horizontal synchronization and vertical synchronization signals when the screen is at the expected location. Once the timing of the horizontal and vertical synchronization signals is accurate, the monitor only needs to keep track of the current location, so it can send the correct colour data to the pixel. Interface: The VGA interface allows the CYCLONE II device of DE2 board to control an external video monitor. This interface is composed of a simple diode-resistor network, DAC, and a 15-pin D-sub connector (labeled VGA), where the monitor can plug into the boards. Three VGA signals are red, green, and blue, while the other two signals are horizontal and vertical synchronization. Manipulating these signals allows write images to the monitor (see Altera DE2 user manual for detailed information).

Practical part:

The simply way to implement the VGA driver called the virtual screen (fig. 4). The size of virtual screen calculates by the following formula: Number of rows = Tscreen/Trow = 16.6 ms / 31.77 us = 524. Pixels in row = Trow/Tpixel = Trow/Tclk = 31.77 us/ 39.722 = 800.

The position of synchronization signals on the virtual screen: horizontal synchronization signal comes low between 658 and 754 pixel; vertical synchronization signal comes low between 493 and 495 row. The colour of invisible area of virtual screen must be black. The current pixel colour provides by RGB method according to table 1. Read 0 0 0 0 1 1 1 1 Green 0 0 1 1 0 0 1 1 Blue 0 1 0 1 0 1 0 1 Colour BLACK BLUE GREEN TURQUOISE RED PURPLE YELLOW WHITE

Table 1: RGB definition The task:


Write the VHDL code of VGA driver that presents on VGA monitor white rectangle (128x128 pixels) on the black background. This rectangle should move from left side of the screen to right side and vice versa (in the centre of vertical alignment). Each movement (left to right and vice versa) must be completed in 1 sec.

Experiment requirements : o Clock 50 MHz Asynchronous reset from DE2 dip-switch o All outputs of design must be registered o Build the block diagram of your VGA driver o Write VHDL RTL code and TB for critical parts of design o Perform synthesis and timing analysis

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