Goals for Lecture

ECE 20B, Winter 2003

Introduction to Electrical Engineering, II
LECTURE NOTES #4 ƒ Systematic simplification using K-maps
Instructor: Andrew B. Kahng (lecture)
Email: [email protected] ƒ Design with NAND and NOR gates
Telephone: 858-822-4884 office, 858-353-0550 cell
Office: 3802 AP&M
Office Hours: MW noon-1pm

Class Website: http://vlsicad.ucsd.edu/courses/ece20b/wi03

Systematic Simplification Example of Prime Implicants

ƒ A Prime Implicant is a product term obtained by ƒ Find ALL Prime Implicants

combining the maximum possible number of adjacent CD ESSENTIAL Prime Implicants
squares in the map. C
BD C BC BD
ƒ A prime implicant is called an Essential Prime Implicant
1 1 1 1 1 1
if it is the only prime implicant that covers (includes)
one or more minterms. BD 1 1
BD 1 1
ƒ Prime Implicants and Essential Prime Implicants can be B B
determined by inspection of a K-map. 1 1 1 1
A A
ƒ A set of prime implicants that "covers all minterms" 1 1 1 1 1 1 1 1
means, for each minterm of the function, at least one AB
prime implicant in the set of prime implicants includes D D
the minterm. AD
3 4

Prime Implicant Example Systematic Approach

1. Find all PIs of the function F.
ƒ F(A,B, C,D) = Σm(0,2,3,8,9 ,10,11,12, 13,14,15) 2. Select all essential PIs, checking off included minterms.
3. Find all less than PIs and delete those that are less than, but not
equivalent to, at least one other PI. (As a result, some of the other
unselected PIs may become essential.)
4. Repeat 2 and 3 until no more less than PIs appear.

5. Find equivalent PIs and select arbitrarily one PI from each set of
equivalent PIs, checking off included minterms.
6. If minterms remain unchecked and no PI less than relations can
be obtained, then a cyclic structure exists. For a cyclic structure,
(a) arbitrarily select a PI and repeat steps 1 through 6, and
(b) delete the same PI selected and repeat steps 1 through 6. Compare
literal cost of the solutions generated and select the minimum literal
cost cover.
7. Discard any redundant (unused) PIs.
5 6

1
 Other PI Selection Example
ƒ Once the Essential Prime Implicants are selected,
Select Essential PIs: Eliminate Less Than Pis:
we need to "prune" the solution set further. To
do this, we determine which can be eliminated by
finding Less Than PIs and Redundant PIs. y y
• Less Than PIs: PIi is said to be Less Than PIj if PIi
contains at least as many literals as PIj and PIj covers at 1 1 1 1 1 1 1 1
least all of the as yet uncovered minterms that PIi
covers. 1 1
• Equivalent PIs: A set of PIs which are pair-wise less x x
than each other. 1 1 1 1 1 1
• Secondary Essential PIs: Once the less than PIs are w w
removed from consideration, new PIs become essential 1 1 1 1
and they are called Secondary Essential PIs.
• Redundant PIs: These are PIs whose minterms have
been completely covered by the PIs selected and are
z z
removed from consideration.

7 8

Example (cont.) Five Variable or More K-maps

ƒ For five variable problems, we use two adjacent K-maps. It
Select Secondary Eliminate Redundant PIs: becomes harder to visualize adjacent minterms for
Essential PIs: selecting PIs. You can extend the problem to six variables
by using four K-maps.
y y v=0 v=1
1 1 1 1 1 1 1 1 y

1 1
x x
1 1 1 1 1 1 x x
w w
1 1 1 1 w w

z z z z

9 10

Don't Cares in K-maps Example: BCD “5 or More”

ƒ Sometimes a function table contains entries for which it is ƒ A function F1(w,x,y,z) which is defined as
known the input values will never occur. In these cases, the "5 or greater" over a BCD input, as below.
output value need not be defined. By placing a “don't care”
in the function table, it may be possible to arrive at a lower Don't cares are on non- BCD values.
cost logic circuit. ƒ F1(w,x,y,z) = w + x z + x y
ƒ “Don't cares” are usually denoted with an "x" in the K-map or y ƒ This is slightly lower in cost than F2
function table. where the don't cares are required to be
ƒ Example of “Don't Cares” - A logic function defined on 4-bit 00 01 03 02 "0".
variables encoded as BCD digits where the four-bit input 04 15 17 16 F2(w,x,y,z) = w x z + w x y + wx y
variables never exceed 9, base 2. Symbols 1010, 1011, 1100, x
1101, 1110, and 1111 will never occur. Thus, we DON'T X12 X13 X15 X14
ƒ For this particular function, note that the
CARE what the function value is for these combinations. w
1 8 1 9 X11 X10 literal cost of the complement of
ƒ “Don't cares“are used in minimization procedures in such a F1(w,x,y,z), meaning "4 or less", is not
way that they may ultimately take on either a 0 or 1 value in z changed by using the don't cares.
the result.
11 12

2
Product of Sums Example NAND and NOR Implementation
ƒ F(A,B, C,D) = Σm(3,9,11,12 ,13,14,15) +Σd (1,4,6) ƒ We can implement general Boolean
equations with three primitives:
ƒ Use F and take complement of result: • AND
• OR
• NOT
ƒ Now, we’ll see that either of two gates, the
NAND gate or the NOR gate, can be used
to implement arbitrary logic functions.
ƒ We use the Positive Logic Convention
(where all signals are active high) and a
small circle to on a symbol to represent
NOT or invert.
13 14

NAND Gates NAND Gates (cont.)

ƒ The basic positive logic NAND gate is denoted by ƒ Applying DeMorgan's Law gives:
• Invert-OR (NAND)
the following symbol:
• AND-Invert (NAND) X
Y F( X , Y , Z ) = X + Y + Z
X Z
Y F( X , Y , Z ) = X Y Z
Z
ƒ We call this symbol for a NAND gate the Invert-OR
ƒ NAND comes from NOT AND, i. e., the AND since all inputs are inverted, followed by the OR
function with a NOT applied. We call this symbol function.
for a NAND gate an AND-Invert. The small circle ƒ Both symbols represent the NAND gate - it is
represents the invert function. sometimes more logically descriptive to use one
form over the other.
ƒ If we apply DeMorgan's Law we get:
ƒ A NAND gate with one input degenerates to an
X Y Z =X +Y +Z inverter.

15 16

NAND Function Implementation NAND Implementation (cont.)

ƒ NAND gates can implement a simplified Sum-of-
In the implementation, note that the bubbles are on
Products form. Constructing two level NAND-
opposite ends of the same line.
NAND gate circuit:
Thus, they can be combined and deleted:
A
A
B
B
G( A, B, C, D ) = A B + C D G(A,B,C,D)
C
C
D
D
ƒ The first level is two 2-input NAND gates using
This form of the implementation is the Sum-of-Products
AND-Invert. The second level is one 2-input
form.
NAND gate using Invert-OR. Using the NAND
relationship, we have:
G( A , B, C, D ) = A B C D
= A B+ C D
= A B + CD
17 18

3
 NAND Implementation (cont.) Degenerate AND Term
ƒ In the implementation, the bubbles are on ƒ The degenerate NAND becomes an
opposite ends of the same line. inverter:
ƒ By X = X , they can be combined and A
deleted: F(A,B,C)
A B
B C
G(A,B,C,D)
C ƒ To implement the complement of F using
D NAND gates, add an inverter to the output:
ƒ A sum
- of- products (SOP) form results A
ƒ To implement an equation like: F(A,B,C) = F'(A,B,C)
A + BC, the NAND for A degenerates to a B
NOT since there is only one input C
19 20

NAND-NAND Example NOR Gates

ƒ Implement: F(w, x, y, z) = y z + w x + x y + w z The basic positive logic NOR gate (Not-OR) is
denoted by the following symbol:
y y
1 1 1 1 1 1 1 1 X
0 1 3 2 0 1 3 2 OR-Invert Y F(X , Y, Z ) = X +Y +Z
1 4
0 5
0 7 1 6
1 4
0 5
0 7 1 6
(NOR) Z
x x
1 12 0 13 0 15 0 14 1 12 0 13 0 15 0 14
w w This is called the OR-Invert, since it is logically an OR
1 1 0 11 0 10 1 1 0 11 0 10
8 9 8 9 function followed by an invert. By DeMorgan's Law
z z we have the following Invert-AND symbol for a NOR
F(w,x,y,z) F’ (w,x,y,z) gate:
X
Invert-AND Y
Z

A single-input NOR gate is an inverter, too.

21 22

NOR Gates NOR Gates (cont.)

ƒ Applying DeMorgan's Law gives:
ƒ The basic positive logic NOR gate is • Invert-AND (NOR)
denoted by the following symbol:
X
• OR-Invert (NOR) Y F( X , Y , Z ) = X ⋅ Y ⋅ Z
X
Z
Y F(X , Y, Z ) = X +Y +Z
Z ƒ We call this symbol for a NOR gate the Invert-AND
ƒ NOR comes from NOT OR, I. e., the OR since all inputs are inverted, followed by the AND
function.
function with a NOT applied. We call this
ƒ Both symbols represent the NOR gate - it is
symbol for a NOR gate an OR- Invert. The sometimes more logically descriptive to use one
small circle represents the invert function. form over the other.
ƒ If we apply DeMorgan's Law we get: ƒ A NOR gate with one input degenerates to an
inverter.
X + Y +Z= X ⋅ Y ⋅ Z
23 24

4
 NOR Function Implementation Graphical Transformations
ƒ NAND gates can implement a simplified Sum-of- The relations from the previous slide lead to the
Products form. Constructing two-level NOR-NOR following transformations:
circuit:
A
B (AB) = ((AB)')' ⇔ (A'+B')'
G( A , B, C, D ) = (A + B )⋅ (C + D )
C (A+B) = ⇔ (A'B')'
D ((A+B)')'
ƒ The first level is two 2-input NOR gates using OR-
(AB)' ⇔ (A'+B')
Invert. The second level is one 2-input NOR gate
using Invert-AND. (A+B)' ⇔ (A'B')
ƒ Using the NOR relationship, we have:
G( A , B, C, D ) =(A+B)+(C+D) Recall that two bubbles in series can be removed
= (A+B)⋅ (C+D) from the circuit
= (A+B)⋅ (C+ D)
25 26

Implementation Example 1 Implementation Example 2

B B Implement the function in AND-NOR.
1
Implement the function in NOR-OR.
1 1 0 1 1 0 1
A 1 1 0 0
A 1 1 0 0
C

We can remove the "Inverter" and replace it with the

complement of the input variable
27 28

Multi-level NAND Implementations Multi-level NAND Example 1

ƒ Add inverters in two-level 15 inputs and 8 gates*
ƒ F = A B’ + A C’ + B A’ + B C’
implementation into the cost picture = A A’ + A B’ + A C’ + B A’ + B B’ + B C’
ƒ Attempt to “combine” inverters to = A (A’ + B’ + C’) + B (A’ + B’ + C’)
reduce the term count 7 inputs and 4 gates
ƒ Attempt to reduce literal + term count A
by factoring expression into POSOP
or SOPOS B F

* Counting inverters (NOTS) as 1 input and 1 gate

29 30