Network-On-Chip Topology: Noc Examples

Download as pdf or txt
Download as pdf or txt
You are on page 1of 5

Network-on-Chip Topology

Ingo Sander
[email protected]

NoC Examples
0 0 1 2 3 1 00 10 20 1 0

4-node ring

2 00 01 02 03 3 10 11 12 13 4 02 20 21 22 23 5 12 22 01 11 21

30

31

32

33

6 03 7 13 23

7 Butterfly with 8 nodes

4x4-Torus
November 19, 2004 2B1447 SoC Architectures

Combined Node consists of Terminal and Switch Node


Switch Node is equivalent to

Direct and Indirect Networks


00 01 02 03

Direct Network
10 11 12 13

Every Node in the network is both a terminal and a switch

20

21

22

23

30

31

32

33

Direct Network

Combined Node Switch Node

Indirect Network
Nodes are either switches or terminal

Indirect Network
November 19, 2004 2B1447 SoC Architectures 3 November 19, 2004 2B1447 SoC Architectures 4

Bisection of a network
A bisection of a network is a cut that partitions the entire network nearly in half The channel bisection of a network is the minimum channel count over all bisections of the network

Bisection
Channel bisection
BC = 4 (2 bidirectional channels go through the bisection)

Bc =

min
bisections

C ( N1 , N 2 )

Bandwidth bisection
BB = 4b (b is the bandwidth of each channel)

4-node ring

The bandwidth bisection of a network is the minimum bandwidth over all bisections of the network

BB =
November 19, 2004

min
bisections

B ( N1 , N 2 )
5 November 19, 2004 2B1447 SoC Architectures 6

2B1447 SoC Architectures

Paths
A path is an ordered set of channels between a source node s and a destination node d The length or hop-count H(s, d) of a path is the number of channels in the path A minimal path is the path with the smallest hop count The diameter of a network Hmax is the largest, minimal hop count over all pairs of terminal nodes in the path The average minimum hop count Hmin is the average hop count over all sources and destinations
November 19, 2004

Throughput
A minimal path (hop-count 2)
00 01

A path (hop-count 4)

02

03

10

11

12

13

20

21

22

23

The throughput of a network is the data rate in bits per second that the networks accepts per input port The topology of a network has a significant impact on the throughput (besides flow control and routing) The ideal throughput is defined as the throughput assuming a perfect routing and flow control
Load is balanced over alternate paths No idle cycles on bottleneck channels

30

31

32

33

4x4-Torus

2B1447 SoC Architectures

Largest minimal path => diameter 6

November 19, 2004

2B1447 SoC Architectures

Thoughput
Maximum throughput occurs, if some channel of the network becomes saturated The channel load of a channel is
the ratio of the bandwidth demanded from the channel to the bandwidth of the input ports (in other words) the amount of traffic that must cross the channel, if each input unit injects one unit of traffic according to the given traffic pattern

Throughput
The ideal throughput ideal is the input bandwidth that saturates the bottleneck channel
ideal = b / max

The channel that carries the largest fraction of the traffic determines the maximum channel load max
November 19, 2004 2B1447 SoC Architectures 9

In general it is difficult to determine the maximum channel load max, but in case for uniform traffic the task is much simpler

November 19, 2004

2B1447 SoC Architectures

10

Another Useful Formula

Another Useful Formula


l L N = H avg C M C L max = M (for M = 1) C

L N l = H avg C M C
L: Load in Network C: Number of Channels N: Number of Nodes M: A packet is emitted each M-th cycle Havg: Average routing distance l: Cycles for a packet from node to node
November 19, 2004 2B1447 SoC Architectures 11 November 19, 2004

2B1447 SoC Architectures

12

Latency
The latency of the network is the time required for a message to traverse a network, from the the time head arrives at the input port to the time where the tail of the mesage departs the output port Latency depends not only on topology, but also on routing, flow control and the design of the router Here the focus lies on topology
November 19, 2004 2B1447 SoC Architectures 13

Latency
There are two latency components:
Head latency Th : Time required for head of the message to traverse the network Serialization latency Ts= L/b : Time required for the tail to catch up (time for a message of length L to cross a channel with bandwidth b)

November 19, 2004

2B1447 SoC Architectures

14

Head Latency
Head latency depends on two topology factors
Router delay Tr (time spent in the routers) and time of flight Tw (time spent on wires) Tr = Havg tr Tw = Dmin / v (average distance Dmin , propagation velocity)

Latency
Together this gives:
T = Havg tr + Dmin / v + L / b

Clearly Havg, Dmin, and b are to a large extent determined by the topology If there is congestion in the network there is a forth term TC

November 19, 2004

2B1447 SoC Architectures

15

November 19, 2004

2B1447 SoC Architectures

16

Latency
Head Tail Arrival at node x tr Leave x txy Arrival at switch y tr Leave y txy Arrival at switch z L/b

Path Diversity
x

A network with multiple minimal paths between most pairs of node is more robust than a network that has only one single route between the nodes

November 19, 2004

2B1447 SoC Architectures

17

November 19, 2004

2B1447 SoC Architectures

18

Path Diversity
0 0 00 1 10 20 1

Path Diversity
In the torus there are several minimal paths to go, if the source and destination are not adjacent

Connections with the source node 2,3,6 or 7 and the destination 4 or 5 will always have to cross the connection between switch 13 and 22. Thus there is a clear risk for congestion in the butterfly network
November 19, 2004

2 01 3 11 21

00

01

02

03

10

11

12

13

4 02 5 12 22

4 20 5 30 31 32 33 21 22 23

6 03 7 Butterfly with 8 nodes 13 23

4x4-Torus

2B1447 SoC Architectures

19

November 19, 2004

2B1447 SoC Architectures

20

You might also like