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Assignment 2 Embeded System

The document describes the design of a finite state machine memory interface controller with the following: - It interfaces a microprocessor and memory buffer and controls the write enable (WE) and output enable (OE) signals during read and write transactions. - It has inputs RDY and RW from the microprocessor where a new transaction starts with RDY and RW determines if it is a read (RW=1) or write (RW=0) one clock cycle later. - It completes a cycle when RDY is asserted and can begin a new transaction, asserting WE during writes and OE during reads according to its truth table.

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Muhammad Ridzuan Mohamed Iqbal
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132 views

Assignment 2 Embeded System

The document describes the design of a finite state machine memory interface controller with the following: - It interfaces a microprocessor and memory buffer and controls the write enable (WE) and output enable (OE) signals during read and write transactions. - It has inputs RDY and RW from the microprocessor where a new transaction starts with RDY and RW determines if it is a read (RW=1) or write (RW=0) one clock cycle later. - It completes a cycle when RDY is asserted and can begin a new transaction, asserting WE during writes and OE during reads according to its truth table.

Uploaded by

Muhammad Ridzuan Mohamed Iqbal
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 2 You are to design a simple memory interface controller (implemented as a FSM), with the following word specifications:

The controller interfaces a microprocessor and a memory buffer. The controller is used to enable and disable the write enable (we) and the output enable (oe) signals of a memory buffer during read and write transactions, respectively. The inputs to the controller are signal RDY and RW, which are outputs of a microprocessor. A new transaction begins with the assertion of RDY following a completed transaction (or upon a power-up reset). One clock cycle after the commencement of the transaction, the value of RW determines whether it is a read or write transaction. If RW is asserted, then it is a read cycle; otherwise it is a write cycle. A cycle is completed by the assertion of RDY, after which a new transaction can begin. WE are asserted during a write cycle, and OE is asserted during a read cycle. First, obtain the top level block diagram showing the overall system.
NS Y0 rw rdy

Reset
PS y1 State Register y0 oe we

Next Sate Logic

Y1

Output Logic

Microprocessor CLK

Memory Buffer

Truth table shown below are derive from the above statement RW = 1 read cycle, OE = 1 RW = 0 write cycle, WE = 1

RW X 0 1

RDY 0 1 1

WE 0 1 0

OE 0 0 1

Table 1.1: Truth Table

Derive the ASM flowchart (or state diagram) of the required controller.

00/01 01/11 10/11

00/10

00/10

00/10

01/11 01/11

Signal S0 S1 S2 S3

Output (Z) 00 00 10 01

Figure 1.2: State Diagram and Signal Output Table Sketch the functional block diagram of the state machine, labelling clearly all signals.

Figure 1.3: Functional Block diagram

Write the Verilog code of this controller

Figure 1.4 Verilog Code Discussion The output of Verilog code is shown below. The output of the Verilog code satisfies truth table shown in Table 1.1 above. a) When RW = X (dont care) , RDY = 0

Figure 1.5 Output of Verilog code for RW = X (dont care), RDY = 0


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The output shown on negative edge clock (CLK) and positive edge reset (RST) on 20ns scale shows OE = 0 and WE = 0. This satisfies the truth table shown on table 1.1 above. b) When RW = 0 , RDY = 1

Figure 1.6 Output of Verilog code for RW = 0, RDY = 1 The output shown on negative edge clock (CLK) and positive edge reset (RST) on 20ns scale shows OE = 0 and WE = 1. This satisfies the truth table shown on table 1.1 above. c) When RW = 1 , RDY = 1

Figure 1.7 Output of Verilog code for RW = 1, RDY = 1 The output shown on negative edge clock (CLK) and positive edge reset (RST) on 20ns scale shows OE = 1 and WE = 0. This satisfies the truth table shown on table 1.1 above.

Conclusion The objective of the assignment was achieved. The basic understanding of Finite State Machine was achieved. The state diagram using the specification given was achieved. Finally the functionality of memory interface controller was tested and the output result was shown on discussion part of this assignment.
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UNIVERSITI MALAYSIA SARAWAK FACULTY OF ENGINEERING ELECTRONIC ENGINEERING DEPARTMENT

KNK 4083 EMBEDED SYSTEM DESIGN

Assignment 2

Lecturers name: Name :

MR ASRANI BIN HAJI LIT Hillare Francis (21058) Muhammad Ridzuan b Mohamed Iqbal (21632)

Due Date

23rd April 2012

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