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ECE124A F11 HW5 Solutions

This document contains the details of Homework #5 for the course ECE124A VLSI Principles at the University of California, Santa Barbara. It includes 4 problems related to CMOS inverters and ring oscillators. Problem 1 involves analyzing the impact of different temperatures on PMOS and NMOS transistors in an inverter. Problem 2 involves drawing the voltage transfer curve for a circuit with an NMOS transistor and nonlinear load. Problem 3 derives expressions for the output high and low voltages of an NMOS inverter. Problem 4 involves designing a ring oscillator in HSpice and analyzing its period, propagation delay and energy-delay product under different conditions.

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262 views4 pages

ECE124A F11 HW5 Solutions

This document contains the details of Homework #5 for the course ECE124A VLSI Principles at the University of California, Santa Barbara. It includes 4 problems related to CMOS inverters and ring oscillators. Problem 1 involves analyzing the impact of different temperatures on PMOS and NMOS transistors in an inverter. Problem 2 involves drawing the voltage transfer curve for a circuit with an NMOS transistor and nonlinear load. Problem 3 derives expressions for the output high and low voltages of an NMOS inverter. Problem 4 involves designing a ring oscillator in HSpice and analyzing its period, propagation delay and energy-delay product under different conditions.

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Peter Verlangieri
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We take content rights seriously. If you suspect this is your content, claim it here.
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UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles

Homework #5
Jiahao Kang

1. (20) In a typical 2:1 CMOS inverter, if the PMOS can be made to operate at a lower temperature (say 20 degree C) than the NMOS (say 120 degree C), what will be the impact on:
(a) (2) VTC Right (b) (2) VM Increase (c) (2) |Gain| Decrease (d) (2) Delay Increase (e) (2) Power Increase

a) (2) The voltage transfer curve (indicate with a sketch of the VTC)
It shifts to the right due to weaker NMOS devices. Electron mobility reduces for higher temperature. On the other hand, VT 0 GC 2Fp QB 0 Qox , where Fp kT ln N a . So VT 0 GC 2kT ln N a QB 0 Qox .
Cox Cox ni ni Cox Cox

VT increases with T increasing.

b) (2) Inverter switching threshold


VM VTn r VDD VTp 1 r

, where r

k p kn

. Since VTP increases, VTC shifts right, and VM increases.

c) (2) Gain
It also reduces, since the slope of the VTC curve in transition region reduces. When both device operates in low temperature due to sizing ratio VTC is in optimum status (close to ideal case) when NMOS operates in higher temperature, VTC deviates from optimum case. Consider Vin decreases from VDD to 0. In the case of NMOS@120oC and PMOS@20oC, the PMOS will open before the NMOS is totally closed. This situation is worse than NMOS@20oC and PMOS@20oC, in which at the time the PMOS closes, the NMOS opens. So g @ VM will decrease.

d) (2) Delay
Delay increases since the high-to-low transition is slower (higher rise time)

e) (2) Power (both switching and leakage)


Short circuit power increase; leakage current increase (since NMOS operates in higher temperature, switching power does not change if the frequency is fixed.)

f) (5) What can be done to the NMOS to make the inverter symmetric (without changing the temperature)
Increasing the width of NMOS will move VM left which can make the inverter symmetric. 1

Or reduce the threshold voltage of the NMOS also has same effect.

g) (5) Show that the capacitive power consumption (Pcap) of a CMOS inverter is independent of the load capacitance (CL) when operating at its maximum speed.
2 Pcap CLVDD f

;
1 ; Req CL

f max 1/ t p

So, Pcap

2 2 CLVDD VDD . Req CL Req

So, the capacitive power consumption (Pcap) of a CMOS inverter is independent of the load capacitance (CL) when operating at its maximum speed.

2. (20) The circuit below features an NMOS transistor that is coupled to a non-linear load device represented by the shaded box. Accompanying figure shows the I-V characteristic for this nonlinear load device. The family of I-V curves for the NMOS transistor is given below:

(a) (12) Draw the VTC for this circuit.


Firstly, we put these two I-V curves together to find their crosses.

VGS(V) 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5

VDS(V) 2.4 2.0 1.4 1.1 0.8 0.6 0.5 0.45

IDS(mA) 0 0.05 0.15 0.28 0.42 0.50 0.52 0.55 2

So, the VTC is:


2.5
2 1.5 1 0.5 0 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5

(b) (8) This circuit can be used as an alternative to a traditional CMOS inverter (where the nonlinear device is a PMOS transistor). From the concepts discussed thus far in the lecture and from the results of your VTC, what are the disadvantages of this method?
Low swing: The output high and low level are 2.5V and 0.45V, the swing of the signal is smaller than VDD. The noise margin (NML) is small. The logical level is relative to the size of the device. Output resistance is high, so it is sensitive to noise and disturbance. Input resistance is low and it consumes DC input current. Static leakage power

Problem 3
In the NMOS inverter shown in the figure below, GC, Qox, Cox, NA, W1,2 and L1,2 are given. a) Derive the expression (or equation) for calculation of VOH b) Derive the expression (or equation) for calculation of VOL c) Draw the VTC of this inverter qualitatively. d) Compared with CMOS inverter, what are the advantages and disadvantages of this design? VDD,

(a,b) (12)

(c) (4)
Vout Vdd

(d) (4)
Low swing Small noise margin (NML) High Static leakage power

0 Vin

4. (20) (Lab) Ring Oscillator


Referring to Page 34 in Lecture 9, design a ring oscillator by odd-number inverters and test it using HSpice. Use 65nm CMOS transistor model from http://ptm.asu.edu/ and minimum sized 2:1 CMOS. Vdd=1V. In your netlist, define a LOAD capacitance CL=0.1pF for EACH inverter. a) (4) Show the schematic of your design (including the trigger) b) (2) What is the period T of your oscillator? What is the tp of one inverter? c) (2) Find out the energy-delay product (EDP) of the circuit, which is defined as: EDP = Pavg . T2. d) (2) Increase the size of both NMOS and PMOS by 10X. What happens to T and EDP? Is the EDP becoming better and better if we continue increase the size? Explain. e) (2) Decrease VDD to 0.5V. What is T and tp now? Explain the change. Netlist (4) Waveform (4)

Hint: the trigger can be a tri-state gate, a pass-transistor or a transmission gate. Or you can set an initial value.

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