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List of Lab Exercises For VHDL Lab

The document outlines a list of 25 lab exercises for a VHDL lab course covering digital circuit design and implementation using VHDL. The exercises include designing basic digital circuits like adders and multiplexers, sequential logic like flip-flops and counters, finite state machines for vending machines, and more advanced topics like ALU design and barrel shifting. Students are tasked with writing VHDL code to implement the designs and performing functional simulation testing.

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Divyanshu Shekhar
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422 views3 pages

List of Lab Exercises For VHDL Lab

The document outlines a list of 25 lab exercises for a VHDL lab course covering digital circuit design and implementation using VHDL. The exercises include designing basic digital circuits like adders and multiplexers, sequential logic like flip-flops and counters, finite state machines for vending machines, and more advanced topics like ALU design and barrel shifting. Students are tasked with writing VHDL code to implement the designs and performing functional simulation testing.

Uploaded by

Divyanshu Shekhar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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List of Lab Exercises for VHDL Lab (EECP 309B) Jan-May 2012

1.

Introduction to Xilinx ISE 9.2i IDE Tools


Write code in VHDL for

2. Design a Digital circuit to implement a 1 bit full adder circuit.

implementation with architecture of all three types and do functional simulation. For dataflow architecture implement all three types of concurrent statements.

3. Design a Digital circuit to implement a 4 bit full adder circuit.


implementation and do functional simulation.

Write code in VHDL for

4. Design a 8 bit Adder/Subtractor circuit where the operation to be performed can be chosen by an input opr (For subtraction opr=0 and for addition opr=1). Write code in VHDL for
implementation and do functional simulation.

5. Design a Digital circuit to implement a 4:1 Multiplexer with Enable/ Signal. Write code in VHDL
for implementation in dataflow and behavioral architecture and do functional simulation.

6. Design a 2 to 4 decoder with OE/ & E/ signals besides P as polarity input. Write code in VHDL for
implementation in behavioral architecture and do functional simulation.

7. Design a D-Latch, D Flip-Flop, JK F/F, SR F/F & T-Flip-Flop. Write code in VHDL for implementation
in behavioral architecture and do functional simulation.

8. Design a) Four bit PIPO Shift Register b) Four bit SISO shift Register. Write code in VHDL for
implementation in behavioral architecture and do functional simulation.

9. Design a Dual Direction SISO Shift Register which can perform both shift-left and shift-right operations. Write code in VHDL for implementation in behavioral architecture and do functional
simulation.

10. Design a) Four bit Up/Down binary Synchronous Counter b) Four bit BCD UP/Down Counter.
Write code in VHDL for implementation in behavioral architecture and do functional simulation.

11. Design a digital circuit to generate a parity bit corresponding to an 8 bit vector. Implement even parity. Write code in VHDL for implementation in behavioral architecture and do functional
simulation.

12. Design a frequency divider digital circuit which can a) Divide by 4 b) divide by 16. Write code in VHDL for implementation in behavioral architecture and do functional simulation.

13. Design a synchronous sequential circuit which detects the low to high transition of an input signal. Draw State diagram (Mealy & Moore FSM) and write code in VHDL for implementation in behavioral architecture and do functional simulation. 14. Design a synchronous sequential string detector circuit which detects the string pattern 111 of an input signal. Draw State diagram (Mealy & Moore FSM) and write code in VHDL for implementation in behavioral architecture and do functional simulation. 15. Design a synchronous sequential string detector circuit which detects the string pattern 1101 of an input signal. Draw State diagram (Mealy & Moore FSM) using StateCAD tool and get VHDL Code for implementation in behavioral architecture and do functional simulation. 16. Design an asynchronous sequential circuit for a soft-drink vending machine. The vending machine sells Limca Tins costing Rs.3 each. It accepts coins of Rs1/- as input currency. Once three Rs.1/- coins are deposited, one Tin of Limca is dispensed. User can terminate transaction before putting all three coins by pressing button called Cancel, in which case the coins fed in should be returned back and machine should go to reset stage. Draw State diagram (Mealy & Moore FSM) using StateCAD tool and get VHDL Code for implementation in behavioral architecture and do functional simulation. 17. Design an asynchronous sequential circuit for a Candy vending machine. The vending machine sells Candy costing Rs.1/- each. It accepts coins of Rs 0.25 and Rs. 0.50 only as input currency. Candy is dispensed once Rs.1 has been deposited. User can terminate transaction before putting all coins by pressing button called Cancel, in which case the coins fed in should be returned back and machine should go to reset stage. In case of excess payment, change should be returned. Draw State diagram (Mealy & Moore FSM) using StateCAD tool and get VHDL Code for implementation in behavioral architecture and do functional simulation. 18. Design a sequential circuit to generate a signal of an arbitrary nature. Use FSM approach to make a State diagram and then write code in VHDL for implementation and functional simulation. 19. Design an 8 bit adder circuit using functions/ procedures. implementation. Write code in VHDL for

20. Design an Even Parity generator circuit for an 8 bit number using functions/ procedures. Write code in VHDL for implementation. 21. Design a barrel shifter circuit. Write code in VHDL for implementation in behavioral architecture and do functional simulation. 22. Design an 8 bit ALU which can perform the following operations: a) Add /Subtract / Multiply two 8 bit unsigned numbers b) Add /Subtract two 8 bit signed numbers c) Add / Subtract two BCD numbers to give BCD answers d) Increment/Decrement 8 bit Operation

e) Divide a 16 bit number by 8 bit number to generate Quotient & Remainder f) Logical Operations AND/OR/XOR/NOT g) Flags should be affected 23. 24. 25.

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